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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2019-03-18
10:15		 Kagoshima Nishinoomote City Hall (Tanega-shima) CPSY2018-120 DC2018-102 We propose a MPU architecture for PLCs (Programmable Logic Controllers) and its complier. The ideaof the speed-up method... [more] CPSY2018-120 DC2018-102
pp.333-339
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2019-03-18
10:35		 Kagoshima Nishinoomote City Hall (Tanega-shima) CPSY2018-121 DC2018-103 We propose a speed-up method for PLCs (Programmable Logic Controllers) by only modifying program
codes. Ladder diagram ... [more]		 CPSY2018-121 DC2018-103
pp.341-346
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]		 2016-11-28
15:30		 Osaka Ritsumeikan University, Osaka Ibaraki Campus Hardware implementation of PLC Instructions by high level synthesis
Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi (TUT) RECONF2016-43		 The hardware implementation of instruction sequence
is a method to conceal and to protect the intellectual property.
... [more]		 RECONF2016-43
pp.19-24
SDM, ICD 2015-08-24
13:35		 Kumamoto Kumamoto City [Invited Talk] Atom-Switch-Based Programmable Logic Array and ROM
Yukihide Tsuji, X Bai, Makoto Miyamura, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi (NEC), Nobuyuki Sugii (Hitachi), Hiromitsu Hada (NEC) SDM2015-61 ICD2015-30		 We have proposed Nonvolatile Programmable Logic (NPL) and ROM using atom switch. Atom switch has unique properties, such... [more] SDM2015-61 ICD2015-30
pp.19-24
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
15:55		 Kanagawa Hiyoshi Campus, Keio University Obfuscated Hardware Implementation of PLC Instructions with Opaque Predicates
Kazuki Uyama, Naoki Fujieda, Shuichi Ichikawa (Toyohashi Tech.) VLD2014-148 CPSY2014-157 RECONF2014-81		 Tamper-proofing technology for instruction sequences of programmable logic controllers（PLCs）is required to protect trade... [more] VLD2014-148 CPSY2014-157 RECONF2014-81
pp.221-226
VLD, CPSY, RECONF, IPSJ-SLDM 2007-01-17
16:50		 Tokyo Keio Univ. Hiyoshi Campus Converting PLC instruction sequence into logic circuit: implementation and evaluation
Masanori Akinaka, Shuichi Ichikawa (Toyohashi Univ. Tech.) 		By implementing a control program with hard-wired logic using reconfigurable devices (e.g., FPGA), a flexible and highly... [more] VLD2006-92 CPSY2006-63 RECONF2006-63
pp.43-48
 Results 1 - 6 of 6  /   
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