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 Results 1 - 14 of 14  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
EMCJ, IEE-EMC, IEE-MAG 2018-11-22
13:40
Overseas KAIST Power Distribution Network (PDN) Modeling of the Perforated Planes in A Silicon Interposer for High Bandwidth Memory (HBM)
Kyungjun Cho, Youngwoo Kim, Subin Kim, Hyunwook Park, Junyong Park, Seongsoo Lee, Joungho Kim (KAIST) EMCJ2018-62
In this paper, we first propose models of the power distribution network (PDN) of perforated power and ground (P/G) plan... [more] EMCJ2018-62
p.21
EMCJ, IEE-EMC, IEE-MAG 2017-05-19
11:15
Overseas Nanyang Technological University Power Distribution Network Virtual Prototyping -- A Demonstration of Pre-layout Design, Simulation & Measurement --
Jun Wu Zhang, Eng Kee Chua, Kye Yak See (NTU) EMCJ2017-18
This work presents a demonstration and validation on Power Distribution Network (PDN) ^virtual prototyping ̄ design proce... [more] EMCJ2017-18
pp.63-66
EMCJ, IEE-EMC, IEE-MAG 2016-06-02
13:42
Overseas NTU, Taiwan [Poster Presentation] Validation of Optimization Method of On-board RL Snubber According to Q Factor
Naoki Kawata, Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2016-27
We proposed RL snubber to damp resonance in power distribution network (PDN) for digital integrated circuits (ICs). RL s... [more] EMCJ2016-27
pp.29-30
EMCJ, IEE-EMC 2014-12-19
15:40
Shizuoka Shizuoka Univ. Flexibility of On-Board RL Snubber for PDN Resonance Damping in terms of Mount Location
Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2014-81
RL snubber had been proposed as a method to damp LC resonances in a power distribution network (PDN) for digital integra... [more] EMCJ2014-81
pp.69-74
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
09:15
Kagoshima   Co-design for reducing power supply noises with On-die PDN Impedance
Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.) CPM2013-109 ICD2013-86
Power integrity is a serious issue in CMOS LSI systems, because power supply noise induces logic instability and electro... [more] CPM2013-109 ICD2013-86
pp.7-12
CAS, NLP 2013-09-26
12:40
Gifu Satellite Campus, Gifu University Efficient Transient Analysis of 3-D Stacked On-Chip Power Distribution Network with Power/Ground Through Silicon Vias by Using Block Latency Insertion Method
Daisei Nagata, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2013-36 NLP2013-48
In this report, we apply the block latency insertion method (block-LIM) to the transient analysis of on-chip power distr... [more] CAS2013-36 NLP2013-48
pp.1-6
CAS, NLP 2013-09-26
13:05
Gifu Satellite Campus, Gifu University Multi-Rate Locally Implicit Latency Insertion Method for Fast Transient Analysis of Power Distribution Network
Takaaki Hojo, Shingo Okada, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2013-37 NLP2013-49
This report describes a multi-rate locally implicit latency insertion method (LILIM) for the fast analysis of power dist... [more] CAS2013-37 NLP2013-49
pp.7-12
EMCJ 2013-07-11
14:25
Tokyo Kikai-Shinko-Kaikan Bldg. Design Method of On-Board RL Snubber Inserted in Power Distribution Network of Integrated Circuits
Ryosuke Yamagata, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2013-34
The power distribution network (PDN) of modern integrated circuits (ICs) have parasitic impedances along power and groun... [more] EMCJ2013-34
pp.39-43
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
13:00
Fukuoka Centennial Hall Kyushu University School of Medicine The Fast Transient Analysis of The Power Distribution Network Modeled by Unstructured Meshes by Using Locally Implicit Latency Insertion Method (LIM)
Shingo Okada, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) VLD2012-96 DC2012-62
This paper describes a locally implicit latency insertion method (LILIM), which is suitable for the fast simulation of a... [more] VLD2012-96 DC2012-62
pp.213-218
EMCJ 2012-04-20
15:35
Ishikawa Kanazawa Univ. RL Damper Circuit for Electoromagnetic Compatibility and Power Integrity of Integrated Circuits
Ryosuke Yamagata, Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2012-8
Resonances of the parasitic impedance in power distribution network (PDN) increase power current in radio frequency that... [more] EMCJ2012-8
pp.43-48
EMCJ, IEE-EMC 2011-10-28
13:50
Aomori Hachinohe Grand Hotel Insertion of Dumping Resistor to Reduce RF IC-Power-Current Peak Caused by Resonance due to Parasitic Impedance
Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2011-84
High-frequency current caused by simultaneous switching of digital gates which leaks toward the DC power supply into the... [more] EMCJ2011-84
pp.29-34
CAS, NLP 2009-09-24
13:25
Hiroshima Hiroshima Univ. Higashi Senda Campus Fast Simulation of Power Distribution Network Based on Semi-Implicit Numerical Integration
Tomoki Ishimaru, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2009-29 NLP2009-65
In this report, a technique to simulate efficiently the power distribution network (PDN) is introduced. In the proposed ... [more] CAS2009-29 NLP2009-65
pp.31-35
EMCJ 2008-12-19
11:15
Gifu Gifu Univ. Compatibility Design of EMI Reduction and Power Integrity by Power Decoupling and Destributed Locating of Capacitors in LSI Power Distribution Network
Hiroshi Tanaka, Osami Wada, Takashi Hisakado (Kyoto Univ.) EMCJ2008-91
Conventionally a strategy of reducing impedance of DC power distribution network (PDN) for LSI has been adopted to impro... [more] EMCJ2008-91
pp.31-36
CPM, ICD 2008-01-18
11:10
Tokyo Kikai-Shinko-Kaikan Bldg [Tutorial Lecture] Survey of Analysis Techniques for On-chip Power Distribution Networks
Takashi Sato (Tokyo Tech.) CPM2007-140 ICD2007-151
Primary techniques and recent trends in power distribution network
(PDN) analysis are reviewed in this paper. Quality ... [more]
CPM2007-140 ICD2007-151
pp.71-76
 Results 1 - 14 of 14  /   
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