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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SS |
2023-03-15 15:40 |
Okinawa |
(Primary: On-site, Secondary: Online) |
SS2022-71 |
Technical debt refers to the extra work that will be incurred in the future as a result of choosing an imperfect solutio... [more] |
SS2022-71 pp.145-150 |
VLD, HWS [detail] |
2022-03-08 09:55 |
Online |
Online |
Wafer-Level Characteristic Variation Modeling with Considering Discontinuous Effect Caused by Manufacturing Equipment Takuma Nagao (National Institute of Technology (KOSEN)), Michihiro Shintani (Nara Institute of Science and Technology), Ken'ichi Yamaguchi, Hiroshi Iwata (National Institute of Technology (KOSEN)), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michiko Inoue (Nara Institute of Science and Technology) VLD2021-92 HWS2021-69 |
Statistical methods for predicting the performance of large-scale integrated circuits (LSIs) manufactured on a wafer are... [more] |
VLD2021-92 HWS2021-69 pp.87-92 |
HWS, VLD |
2019-02-28 15:20 |
Okinawa |
Okinawa Ken Seinen Kaikan |
A SPICE Model Parameter Extraction Environment Using Automatic Differentiation Aoi Ueda (NNCT), Michihiro Shintani (NAIST), Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT), Michiko Inoue (NAIST) VLD2018-117 HWS2018-80 |
Accuracy of circuit simulation highly relys on two techniques: compact modeling and parameter extraction. As increasing ... [more] |
VLD2018-117 HWS2018-80 pp.145-150 |
DC |
2014-02-10 09:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Module Coupling Overhead Aware Scan Chain Construction Meguru Komatsu, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-79 |
It is necessary to minimize the impact on the layout of the design changes to Design for Testability
(DFT). Especially,... [more] |
DC2013-79 pp.1-5 |
DC |
2014-02-10 09:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] |
DC2013-81 pp.13-18 |
DC |
2014-02-10 10:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Suitable Power-Aware Test Pattern Ordering for Deterministic Circular Self Test Path Ryo Ogawa, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-82 |
The power consumption of Very Large Scale Integrated circuit (VLSI) testing is a significant problem. The VLSI should be... [more] |
DC2013-82 pp.19-24 |
DC |
2014-02-10 12:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
An Efficient Test Pattern Generator based on Mersenne Twister algorithm Sayaka Satonaka, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-86 |
To perform a high reliable manufacturing test with a reasonable cost, LFSR is widely used as test pattern generator. How... [more] |
DC2013-86 pp.43-48 |
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