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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, VLD [detail] |
2021-03-03 13:25 |
Online |
Online |
[Memorial Lecture]
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization TaiYu Cheng (Osaka Univ.), Yutaka Masuda (Nagoya Univ.), Jun Nagayama, Yoichi Momiyama (Socionext Inc.), Jun Chen, Masanori Hashimoto (Osaka Univ.) VLD2020-72 HWS2020-47 |
This paper proposes a design optimization methodology that can achieve a mode-wise voltage scalable (MWVS) design with a... [more] |
VLD2020-72 HWS2020-47 p.30 |
DC, CPSY, IPSJ-ARC [detail] |
2019-06-11 16:20 |
Kagoshima |
National Park Resort Ibusuki |
CPSY2019-8 DC2019-8 |
[more] |
CPSY2019-8 DC2019-8 pp.63-68 |
RECONF |
2018-05-25 15:10 |
Tokyo |
GATE CITY OHSAKI |
RECONF2018-5 |
(To be available after the conference date) [more] |
RECONF2018-5 pp.21-26 |
VLD |
2017-03-02 13:55 |
Okinawa |
Okinawa Seinen Kaikan |
[Invited Talk]
IP Timing Constraints Promotion Challenges
-- A method to automatically generate SoC Timing Constraints -- Tatsuya Nakae, Ichiro Shiihara (Socionext) VLD2016-116 |
It is common that recent SoC is integrated with more than 10 functional IPs which are not only in-house designs but also... [more] |
VLD2016-116 p.81 |
CAS, ICTSSL |
2017-01-26 15:20 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Study of Jitter Generator with Digital Control for High-Speed I/O Interface Circuit Yuki Ozawa, Haruo Kobayashi (Gunma Univ.), Ryoji Shiota (Socionext) CAS2016-91 ICTSSL2016-45 |
[more] |
CAS2016-91 ICTSSL2016-45 pp.69-72 |
CAS, NLP |
2016-10-27 15:25 |
Tokyo |
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Self-Calibration and Trigger Circuit for 2-Step SAR TDC Takashi Ida, Yuki Ozawa, Richen Jiang, Haruo Kobayashi (Gunma Univ.), Ryoji Shiota (socionext) CAS2016-48 NLP2016-74 |
This paper presents a 2-step successive-approximation-register time-to-digital converter (SAR TDC) architecture with its... [more] |
CAS2016-48 NLP2016-74 pp.55-60 |
VLD |
2016-03-01 14:45 |
Okinawa |
Okinawa Seinen Kaikan |
IP Design using High-Level Synthesis Design Flow Masato Tatsuoka, Ken Imanishi, Hidenori Nakaishi, Takeshi Toyoyama (SNI) VLD2015-126 |
In this paper we will describe practical experiences about the use of high level synthesis technologies to achieve highe... [more] |
VLD2015-126 pp.87-92 |
SDM |
2015-11-05 11:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Impact of Deep P-Well Structure on Single Event Latchup in Bulk CMOS Takashi Kato, Hideya Matsuyama (SNI) SDM2015-85 |
[more] |
SDM2015-85 pp.7-11 |
ICD, IE, VLD, IPSJ-SLDM [detail] |
2015-10-27 13:50 |
Miyagi |
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[Invited Talk]
High-level Video Analytics PC Subsystem
-- Computer Vision Engine and Heterogeneous Multi-core SoC -- Yukihiro Sasagawa (Socionext) VLD2015-37 ICD2015-50 IE2015-72 |
[more] |
VLD2015-37 ICD2015-50 IE2015-72 pp.69-72 |
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