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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 73  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] 2021-01-26
12:45
Online Online SLM based FPGA-IP soft core
Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) VLD2020-61 CPSY2020-44 RECONF2020-80
In the recent edge computing infrastructure, MEC (Multi-access Edge Computing) devices is considered to reduce the load ... [more] VLD2020-61 CPSY2020-44 RECONF2020-80
pp.125-130
RECONF 2019-05-09
16:35
Tokyo Tokyo Tech Front A case study of an FPGA implementation for streaming data filtering
Hiroki Nakagawa, Yasutaka TsuTsumi, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2019-8
With the spread of IoT (Internet of Things) equipment in recent years, collection of big data becomes easy, and the dema... [more] RECONF2019-8
pp.41-46
RECONF 2018-09-17
14:30
Fukuoka LINE Fukuoka Cafe Space A Case Study on Complex Event Processing over low cost ARM+FPGA Boards.
Hendarmawan (Kumamoto University), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto University) RECONF2018-21
 [more] RECONF2018-21
pp.13-18
RECONF 2018-09-18
15:15
Fukuoka LINE Fukuoka Cafe Space A case study of database filtering on streaming processing
Hiroki Nakagawa, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2018-33
With the spread of IoT (Internet of Things) equipment in recent years, collection of big data becomes easy, and the dema... [more] RECONF2018-33
pp.79-84
RECONF 2018-05-24
14:30
Tokyo GATE CITY OHSAKI Visibility study of CNN implementation using High Speed Serial Optical Interconnection
Juntaro Chikama, Yasuhiro Nakahara, Motoki Amagasaki, Morihiro Kuga, Msahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2018-7
In this research, we realize a low power consumption and scalable system by implementing CNN on multi FPGA system.To sol... [more] RECONF2018-7
pp.33-38
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-19
13:00
Kanagawa Raiosha, Hiyoshi Campus, Keio University FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights
Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2017-82 CPSY2017-126 RECONF2017-70
Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Field Programmable Gat... [more] VLD2017-82 CPSY2017-126 RECONF2017-70
pp.119-124
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-06
10:30
Kumamoto Kumamoto-Kenminkouryukan Parea hCODE 2.0: An Open-source Platform for FPGA Cluster System
Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2017-27 DC2017-33
In recent years, major cloud providers such as Amazon and Microsoft are improving cloud applications using FPGAs.
By in... [more]
VLD2017-27 DC2017-33
pp.1-6
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-06
13:25
Kumamoto Kumamoto-Kenminkouryukan Parea RECONF2017-38 Graph processing has memory access with low locality, and it is not easy to process large-scale graphs which have the mi... [more] RECONF2017-38
pp.7-12
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:50
Kumamoto Kumamoto-Kenminkouryukan Parea Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking
Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2017-42
In recent years,Three-dimensional (3D) field-programmable gate arrays(FPGAs) are expected to offer higher logic density ... [more] RECONF2017-42
pp.31-36
RECONF 2017-09-26
13:55
Tokyo DWANGO Co., Ltd. A case study of High-level Synthesis Using Higher-order Function on Functional Language
Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-35
The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forc... [more] RECONF2017-35
pp.75-80
RECONF, CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-05-22
16:20
Hokkaido Noboribetsu-Onsen Dai-ichi-Takimoto-Kan CNN implementation on FPGA with Power of 2 Approximation of Weight
Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-6
Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Considering CNN implem... [more] RECONF2017-6
pp.25-30
RECONF, CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-05-22
17:10
Hokkaido Noboribetsu-Onsen Dai-ichi-Takimoto-Kan A proposal of Bit Serial Arithmetic Units for Arbitrary Precision
Tomonori Miura, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-8
In this paper,we propose a bit serial arithmetic unit for arbitrary precision.It calculates 1 digit ev- ery cycle from t... [more] RECONF2017-8
pp.37-41
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] 2017-01-23
15:20
Kanagawa Hiyoshi Campus, Keio Univ. Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection
Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2016-75 CPSY2016-111 RECONF2016-56
We propose a multiple FPGA system using high speed optical serial interconnection for a inter-connection of FPGAs. In th... [more] VLD2016-75 CPSY2016-111 RECONF2016-56
pp.31-36
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-29
10:55
Osaka Ritsumeikan University, Osaka Ibaraki Campus Development of power estimation tool for three dimensional FPGA
Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-46
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] RECONF2016-46
pp.35-40
RECONF 2016-09-06
10:55
Toyama Univ. of Toyama A Study of Methodology and Tools for Open-source FPGA Accelerators
Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-34
Today's information and communication society requires more and higher-performance computing devices with the constraint... [more] RECONF2016-34
pp.45-50
VLD, IPSJ-SLDM 2016-05-11
13:50
Fukuoka Kitakyushu International Conference Center Multi bit soft error tolerant FPGA architecture
Yuji Nakamura, Takuya Teraoka, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2016-3
Due to reaching the nanoscale transistor size, effect of soft error to the memory has become conspicuous. In small devic... [more] VLD2016-3
pp.35-40
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
11:05
Kanagawa Hiyoshi Campus, Keio University FPGA routing structure based on H-Tree topology
Yuki ishii, Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2015-78 CPSY2015-110 RECONF2015-60
FPGA(Fiele Programmable Gate Array) has many routing resources in order to provide the flexibility. These routing resour... [more] VLD2015-78 CPSY2015-110 RECONF2015-60
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
11:15
Nagasaki Nagasaki Kinro Fukushi Kaikan A Study of HW/SW Co-design Framework based on the Virtualization Technology
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-52
One challenge for the heterogeneous computing with the FPGA is to bridge the development gap between SW and HW design. T... [more] RECONF2015-52
pp.21-26
RECONF 2015-09-18
09:25
Ehime Ehime University Trax solver based on machine-learned evaluation function
Takuya Nakamichi, Yusuke Sonoda, Takayuki Matsuzaki, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2015-33
We develop a solver of board game Trax. Our basic strategy is a common game tree search algorithm. We explore the best m... [more] RECONF2015-33
pp.7-12
RECONF 2015-06-19
12:00
Kyoto Kyoto University An Area Optimization of 3D FPGA with high speed inter-layer communication link
Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-4
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] RECONF2015-4
pp.17-22
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