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All Technical Committee Conferences (Searched in: Recent 10 Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2024-09-18 14:15 |
Niigata | (Primary: On-site, Secondary: Online) |
Shell-Role style FPGA chip SLMLET-2 for IoT applications Hideharu Amano, Takuya Kojima (U. Tokyo), Morihiro Kuga (Kumamoto Univ.), Hayate Okuhara (NUS), Masahiro Iida (Kumamoto Univ.)  RECONF2024-54 |
In recent years, efforts have been underway to enhance the functionality and performance of IoT edge devices, aiming to ... [more] | RECONF2024-54 pp.60-65 |
| RECONF | 2024-09-18 14:40 |
Niigata | (Primary: On-site, Secondary: Online) |
Development of improved eFPGA-IP for MEC devices Zhan Yan, Koudai Takeno, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) RECONF2024-55 |
The authors are developing an FPGA (Field Programmable Gate Array)-IP for MEC (Multi-access Edge Computing) devices, whi... [more] | RECONF2024-55 pp.66-71 |
| RECONF | 2024-09-18 15:05 |
Niigata | (Primary: On-site, Secondary: Online) |
Consideration of floorplan of DSP block in FPGA-IP for MEC device Kodai Takeno, Zhan Yan, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) RECONF2024-56 |
The authors are developing FPGA-IP to be embedded in chips as part of their research on MEC (Multi-access Edge Computing... [more] | RECONF2024-56 pp.72-78 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-17 14:10 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic Souhei Takagi, Takuya Kozima, Hideharu Amano (Keio Univ), Morihiro Kuga, Masahiro Iida (Kumamoto Univ) VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 |
SLM (Scalable Logic Module) is a fine-grained reconfigurable logic developed by Kumamoto University, characterized by it... [more] | VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 pp.215-220 |
| RECONF | 2023-09-15 14:15 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Library Development for RISC-V FPGA SoCs Takuya Kojima (UTokyo/JST PRESTO), Yosuke Yanai (Keio Univ.), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) RECONF2023-31 |
[more] | RECONF2023-31 pp.52-57 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-04 18:20 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ./JST PRESTO), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) CPSY2023-25 DC2023-25 |
In recent years, opportunities requiring processing at the IoT edge have been increasing. As a solution, not only conven... [more] | CPSY2023-25 DC2023-25 pp.100-105 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 12:45 |
Online | Online | SLM based FPGA-IP soft core Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) VLD2020-61 CPSY2020-44 RECONF2020-80 |
In the recent edge computing infrastructure, MEC (Multi-access Edge Computing) devices is considered to reduce the load ... [more] | VLD2020-61 CPSY2020-44 RECONF2020-80 pp.125-130 |
| RECONF | 2019-05-09 16:35 |
Tokyo | Tokyo Tech Front | A case study of an FPGA implementation for streaming data filtering Hiroki Nakagawa, Yasutaka TsuTsumi, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2019-8 |
With the spread of IoT (Internet of Things) equipment in recent years, collection of big data becomes easy, and the dema... [more] | RECONF2019-8 pp.41-46 |
| RECONF | 2018-09-17 14:30 |
Fukuoka | LINE Fukuoka Cafe Space | A Case Study on Complex Event Processing over low cost ARM+FPGA Boards. Hendarmawan (Kumamoto University), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto University) RECONF2018-21 |
[more] | RECONF2018-21 pp.13-18 |
| RECONF | 2018-09-18 15:15 |
Fukuoka | LINE Fukuoka Cafe Space | A case study of database filtering on streaming processing Hiroki Nakagawa, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2018-33 |
With the spread of IoT (Internet of Things) equipment in recent years, collection of big data becomes easy, and the dema... [more] | RECONF2018-33 pp.79-84 |
| RECONF | 2018-05-24 14:30 |
Tokyo | GATE CITY OHSAKI | Visibility study of CNN implementation using High Speed Serial Optical Interconnection Juntaro Chikama, Yasuhiro Nakahara, Motoki Amagasaki, Morihiro Kuga, Msahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2018-7 |
In this research, we realize a low power consumption and scalable system by implementing CNN on multi FPGA system.To sol... [more] | RECONF2018-7 pp.33-38 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 13:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2017-82 CPSY2017-126 RECONF2017-70 |
Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Field Programmable Gat... [more] | VLD2017-82 CPSY2017-126 RECONF2017-70 pp.119-124 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 10:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | hCODE 2.0: An Open-source Platform for FPGA Cluster System Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2017-27 DC2017-33 |
In recent years, major cloud providers such as Amazon and Microsoft are improving cloud applications using FPGAs. By in... [more] |
VLD2017-27 DC2017-33 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | RECONF2017-38 |
Graph processing has memory access with low locality, and it is not easy to process large-scale graphs which have the mi... [more] | RECONF2017-38 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2017-42 |
In recent years,Three-dimensional (3D) field-programmable gate arrays(FPGAs) are expected to offer higher logic density ... [more] | RECONF2017-42 pp.31-36 |
| RECONF | 2017-09-26 13:55 |
Tokyo | DWANGO Co., Ltd. | A case study of High-level Synthesis Using Higher-order Function on Functional Language Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-35 |
The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forc... [more] | RECONF2017-35 pp.75-80 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 16:20 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | CNN implementation on FPGA with Power of 2 Approximation of Weight Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-6 |
Convolutional Neural Network (CNN), a method of Image recognition, is utilized in various fields. Considering CNN implem... [more] | RECONF2017-6 pp.25-30 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 17:10 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | A proposal of Bit Serial Arithmetic Units for Arbitrary Precision Tomonori Miura, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-8 |
In this paper,we propose a bit serial arithmetic unit for arbitrary precision.It calculates 1 digit ev- ery cycle from t... [more] | RECONF2017-8 pp.37-41 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-23 15:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2016-75 CPSY2016-111 RECONF2016-56 |
We propose a multiple FPGA system using high speed optical serial interconnection for a inter-connection of FPGAs. In th... [more] | VLD2016-75 CPSY2016-111 RECONF2016-56 pp.31-36 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:55 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Development of power estimation tool for three dimensional FPGA Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-46 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2016-46 pp.35-40 |
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