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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, SDM | 2014-08-04 13:55 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
STT-MRAM Development for Embedded Cache Memory Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP)  SDM2014-68 ICD2014-37 |
We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration ... [more] | SDM2014-68 ICD2014-37 pp.35-38 |
| SDM | 2012-03-05 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Basic Performance of a Logic-IP Compatible eDRAM with Cylinder Capacitors in Low-k/Cu BEOL Layers Ippei Kume, Naoya Inoue, Ken'ichiro Hijioka, Jun Kawahara, Koichi Takeda, Naoya Furutake, Hiroki Shirai, Kenya Kazama, Shin'ichi Kuwabara, Msasatoshi Watarai, Takashi Sakoh, Toshifumi Takahashi, Takashi Ogura, Toshiji Taiji, Yoshiko Kasama (Renesas Electronics) SDM2011-177 |
We have confirmed the basic performance of a Logic-IP compatible (LIC) eDRAM with cylinder capacitors in the low-k/Cu BE... [more] | SDM2011-177 pp.7-11 |
| ICD | 2011-04-18 10:50 |
Hyogo | Kobe University Takigawa Memorial Hall | [Invited Talk]
A Technical Trend and Embedded DRAM Technology for High-Performance NAND Flash Memories Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii (Toshiba) ICD2011-2 |
In this paper, first, the technical trend for high-bandwidth NAND flash memories is introduced. Second, an embedded DRAM... [more] | ICD2011-2 pp.7-12 |
| ICD | 2008-04-17 11:15 |
Tokyo | [Invited Talk]
An 833MHz Pseudo Two-Port Embedded DRAM for Graphics Applications Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka (Toshiba) ICD2008-3 |
This paper describes a pseudo two-port embedded DRAM macro developed for graphics applications. It introduces read/write... [more] | ICD2008-3 pp.13-18 |
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| ICD | 2008-04-17 13:05 |
Tokyo | [Invited Talk]
Embedded DRAM Technology for Consumer Electronics Hiroki Shirai, Ryousuke Ishikawa, Yuichi Itoh, Takuya Kitamura, Mami Takeuchi, Takashi Sakoh, Ken Inoue, Tohru Kawasaki, Nobuyuki Katsuki, Hiroyuki Hoshizaki, Shinichi Kuwabara, Hidetaka Natsume, Masato Sakao, Takaho Tanigawa (NEC Electronics) ICD2008-4 |
This paper presents embedded DRAM device technology utilizing stacked MIM(Metal-Insulator-Metal) capacitor. Targeted for... [more] | ICD2008-4 pp.19-24 |
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| ICD, ITE-IST | 2007-07-26 17:05 |
Hyogo | Low power consumption of H.264/AVC decoder with dynamic voltage and frequency scaling Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-52 |
We propose an elastic pipeline architecture that can apply dynamic voltage scaling (DVS) to a dedicated hardware, and ap... [more] | ICD2007-52 pp.89-94 |
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| ICD | 2007-04-12 10:40 |
Oita | Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor Takaho Tanigawa, Yasushi Yamagata, Hiroki Shirai, Hirotoshi Sugimura, Tomoko Wake, Ken Inoue, Takashi Sakoh, Masato Sakao (NECEL) ICD2007-4 |
This paper presents embedded DRAM device technology utilizing stacked MIM(Metal-Insulator-Metal) capacitor. Targeted for... [more] | ICD2007-4 pp.17-22 |
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| ICD | 2006-04-13 09:45 |
Oita | Oita University | A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode Tomohisa Takai, Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Naoko Itoga, Takayuki Miyazaki (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano (Toshiba) |
An Extended Data Retention (EDR) sleep mode with on-chip ECC and the MT-CMOS technique is proposed for the embedded DRAM... [more] | ICD2006-2 pp.7-12 |
| ICD, SDM | 2005-08-19 13:25 |
Hokkaido | HAKODATE KOKUSAI HOTEL | 0.5V Asymmetric Three-Tr. Cell (ATC) DRAM Using 90nm Generic CMOS Logic Process Motoi Ichihashi, Haruki Toda, Yasuo Itoh, Koichiro Ishibashi (STARC) |
Asymmetric Three-Tr. Cell (ATC) DRAM which has one P- and two N-MOS transistors for one unit cell is proposed with "forc... [more] | SDM2005-151 ICD2005-90 pp.49-54 |
| ICD | 2005-04-14 11:40 |
Fukuoka | A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda (Toshiba), Tomoki Higashi (Toshiba Microelectronics), Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe (Toshiba) |
We report on a 128Mbit DRAM design using the capacitor-less DRAM cell or the floating body cell(FBC) on SOI. The cell of... [more] | ICD2005-5 pp.23-28 |
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| ICD | 2005-04-14 13:00 |
Fukuoka | [Invited Talk]
* Hiroyuki Yamauchi (Matsushita) |
Based on the actual examples of where, how and why each memory is used, the representative embedded memories are classif... [more] | ICD2005-6 pp.29-34 |
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| ICD | 2005-04-15 11:30 |
Fukuoka | Burst-Cycle Data Compression Schemes for Pre-Fuse Wafer-Level Test in Large Scale High-Speed embedded DRAM Ryo Fukuda, Kenji Kobayashi (Toshiba Corp.), Masashi Akamatsu, Minoru Kaihatsu, Atsushi Tamura, Kazuo Taniguchi (Sony Corp.), Yohji Watanabe (Toshiba Corp.) |
This paper describes two novel data compression schemes suitable for high density and high speed embedded DRAMs. The par... [more] | ICD2005-15 pp.13-17 |
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