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 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CCS, NLP 2023-06-09
13:30		 Tokyo Tokyo City Univ. Bifurcation analysis and simulation of a biological switch model
Quankai Zhang, Tetsushi Ueta (Tokushima Univ) NLP2023-23 CCS2023-11		 Using a mathematical model of biological switches, we examine the phenomenon of cell differentiation under a cyclic exte... [more] NLP2023-23 CCS2023-11
pp.45-48
DC 2022-03-01
10:55		 Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)		 On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement
Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT) DC2021-67		 It is effective for aging of a logic circuit to measure a circuit delay periodically in field. In order to compare the d... [more] DC2021-67
pp.18-23
DC 2019-12-20
16:30		 Wakayama   Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test
Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85		 Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] DC2019-85
pp.37-42
DC 2018-12-14
13:00		 Okinawa Miyako Seisyonen-No-Ie On-Chip Delay Measurement for In-field Periodic Test of FPGAs
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2018-58		 Delay-related failures due to aging phenomena are a critical issue of state-of-the-art VLSI systems. In order to detect ... [more] DC2018-58
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
10:50		 Nagasaki Nagasaki Kinro Fukushi Kaikan On Correction of Temperature Influence to Delay Measurement in FPGAs
Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) VLD2015-63 DC2015-59		 As a means for delay testing for VLSIs in field, a measurement method of a path delay for a logic circuit using variable... [more] VLD2015-63 DC2015-59
pp.165-170
DC 2012-06-22
15:45		 Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg An Evaluation of Low Power BIST Method
Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara (Kyutech) DC2012-14		 Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophi... [more] DC2012-14
pp.33-38
 Results 1 - 6 of 6  /   
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