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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 14:50 |
Online | Online | Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT)  VLD2021-57 CPSY2021-26 RECONF2021-65 |
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] | VLD2021-57 CPSY2021-26 RECONF2021-65 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 12:05 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II Yusuke Hatori, Kohei Osawa (Keio Univ.), Keigo Mizotani (Nintendo), Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.) CPSY2015-75 |
Recent embedded real-time systems have required multiprocessors to achieve not only real-time con- straints but also hi... [more] |
CPSY2015-75 pp.81-86 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-06 14:50 |
Kagoshima | A Resource Utilization Aware Method to Improve Throughput on RMT Processor Taro Murata, Kensuke Kaneda, Masayoshi Takasu, Keigo Mizotani, Yusuke Hatori, Nobuyuki Yamasaki (Keio Univ.) CPSY2014-166 DC2014-92 |
SMT (Simultaneous MultiThreading) architecture is suitable for embedded processors which have area constraints, it is b... [more] |
CPSY2014-166 DC2014-92 pp.25-30 |
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| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 16:30 |
Kanagawa | Hiyoshi Campus, Keio University | A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.) VLD2014-149 CPSY2014-158 RECONF2014-82 |
In recent embedded real-time systems, there are many systems with both hard real-time tasks and soft real-time tasks. Wh... [more] | VLD2014-149 CPSY2014-158 RECONF2014-82 pp.227-232 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Proposal of Speculative Memory Access Mechanism Based on Snoop Cache Yuji Sekiguchi, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2012-47 |
Ratio of execution path is mostly dominated by up to two execution paths in program loops. We have developed the specula... [more] | CPSY2012-47 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 14:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Study of Path Prediction Mechanism for Improving Accuracy by using Detailed History Information Hiroyoshi Jutori, Takanobu Baba, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) CPSY2012-48 |
Speculative multithreading expects speed-up for programs that have complicated dependency. To achieve high performance ... [more] |
CPSY2012-48 pp.7-12 |
| DC, CPSY (Joint) |
2012-08-02 13:30 |
Tottori | Torigin Bunka Kaikan | Effect of Loop Unrolling for Two-Path Limited Speculation Method Yuki Homma, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2012-9 |
Our Two-Path Limited Speculation system PALS speculatively executes one of the top two paths of high frequency in loops.... [more] | CPSY2012-9 pp.1-6 |
| DC, CPSY (Joint) |
2011-07-29 11:35 |
Kagoshima | A Study of Dynamic Modification of Optimal Paths Speculation for Two-Path Limited Speculation Method Hiroyoshi Jutori (Utsunomiya Univ.), Tsubasa Tsuda (SKI Co.,Ltd.), Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2011-14 |
Thread-level speculative execution expects speed-up for programs that have complicated dependency. We focus on a change... [more] |
CPSY2011-14 pp.31-36 |
|
| CPSY, DC (Joint) |
2010-08-03 - 2010-08-05 |
Ishikawa | Kanazawa Cultural Hall | A Consideration of Speculative Memory Access in Two-Path Limited Speculation System Hiroyoshi Jutori, Akihiro Fukuda, Tsubasa Tsuda, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2010-18 |
We have proposed two-path limited speculation method and a multi-core processor architecture PALS which based on the met... [more] | CPSY2010-18 pp.61-66 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 11:20 |
Kochi | Kochi City Culture-Plaza | Proposal of Multi-Core Processor PALS to Realize Two-Path Limited Speculation Method Hiroyoshi Jutori, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2009-46 |
We have proposed a two-path limited speculation method for higher performance execution of program's loop. This method s... [more] | CPSY2009-46 pp.19-24 |
| RECONF | 2009-09-17 16:40 |
Tochigi | Utsunomiya Univ. | [Invited Talk]
YAWARA: A Self-Optimizing Computer System Project Takanobu Baba, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) RECONF2009-27 |
The YAWARA project aims at an extreme optimization system that reconfigures both hardware and software at run-time. This... [more] | RECONF2009-27 pp.49-54 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | Pipelined Multithreading with Clustered Communication on Commodity Multi-Core Processors *Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2009-26 |
Recently proposed pipelined multithreading (PMT) techniques have shown great applicability to parallelizing general prog... [more] | CPSY2009-26 pp.97-102 |
|
| VLD | 2009-03-12 15:40 |
Okinawa | A Task Mapping Algorithm for Task Chaining Network Processor by Backtracking Keita Saito, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-151 |
To meet increasing demands of link speeds and complex network applications, network processor is required because it has... [more] | VLD2008-151 pp.147-152 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:00 |
Fukuoka | Kitakyushu Science and Research Park | A Path-Based Thread Partitioning Technique Considering Loop Structures Hirohito Ogawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2008-37 |
Speed-up by the multithreaded execution is important to make use of the performance of the multi-core processor effect... [more] |
CPSY2008-37 pp.1-6 |
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