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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online | Online | Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS)  VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 |
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] | VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 pp.19-24 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| VLD, IPSJ-SLDM | 2010-05-19 17:00 |
Fukuoka | Kitakyushu International Conference Center | Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architecture Hiroshi Yuasa, Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2010-4 |
Advancing CMOS process technology implies decreasing operating voltages, leaving LSI increasingly vulnerable to temporar... [more] | VLD2010-4 pp.37-42 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-26 14:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Design of Reconfigurable Logic Device based on Variable Grain Logic Cell Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2009-79 CPSY2009-61 RECONF2009-64 |
We propose a variable grain logic cell（VGLC）architecture. Its key feature is variable granularity which helps to create ... [more] | VLD2009-79 CPSY2009-61 RECONF2009-64 pp.59-64 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:40 |
Fukuoka | Kitakyushu Science and Research Park | Coarse-Grained Reconfigurable Architecture with Flexible Reliability Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2008-73 DC2008-41 |
Acceptable soft error rate on a VLSI chip varies depending on applications and operating environment so that recent VLSI... [more] | VLD2008-73 DC2008-41 pp.79-84 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:00 |
Fukuoka | Kitakyushu Science and Research Park | A Study of Local Interconnect Architecture for Variable Grain Logic Cell Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-42 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-42 pp.21-26 |
| RECONF | 2008-09-26 10:30 |
Okayama | Okayama Univ. | Exploration of Input Granularity Optimization for Variable Grain Logic Cell Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-33 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | RECONF2008-33 pp.63-68 |
| RECONF | 2008-05-22 16:05 |
Fukushima | The University of Aizu | A Novel Cluster Structure for Variable Grain Logic Cell Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-8 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-8 pp.43-48 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 15:35 |
Fukuoka | Kitakyushu International Conference Center | A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-33 |
Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained types, its structure can ... [more] |
RECONF2007-33 pp.7-12 |
| RECONF | 2007-05-17 16:10 |
Ishikawa | Kanazawa Bunka Hall | Performance Evaluation of Variable Grain Logic Cell for Arithmetic Circuits Yoshiaki Satou, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-7 |
Reconfigurable logic devices are classified into two type of logic block, which are coarse-grain and fine-grain by the b... [more] | RECONF2007-7 pp.37-42 |
| RECONF | 2006-05-18 11:30 |
Miyagi | TOHOKU UNIVERSITY | A Retargetable Compiler for Cell-Array Based Self-Reconfigurable Architecture Masayuki Hiromoto, Shin'ichi Kouyama, Kentaro Nakahara, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
Simulation-based quantitative performance evaluation using specific applications is indispensable for developing archite... [more] | RECONF2006-2 pp.7-12 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-25 10:00 |
Kanagawa | Reconfigurable 1-bit processor array with reduced wiring area Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST) |
Semiconductor makers have a problem of how to reduce the production cost. Because of the increasing gates to implement a... [more] | VLD2004-98 CPSY2004-64 pp.7-12 |
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