Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2007-1
Memory Assignment Method for Matrix Processing Array
Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas)
pp. 1 - 6
VLD2007-2
Heuristic Instruction Scheduling Method for Processors with Partial Data Forwarding Structure
Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 7 - 12
VLD2007-3
Reconfigurable Architecture with Caluculation Function for Shift Keying
Ayataka Kobayashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 13 - 18
VLD2007-4
A Modeling of Dynamically Reconfigurable Processor using SystemC
Kouji Ueda, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aidu)
pp. 19 - 24
VLD2007-5
An Architecture Design and its Evaluation for Speech Recognition System
Joh Hashimato, Makoto Saitsuji, Takashi Kambe (Kinki Univ.)
pp. 25 - 30
VLD2007-6
[Panel Discussion]
Highlevel synthesis; will it be useful or useless?
Masahiro Fukui (Ritsumeikan Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Tomonori Izumi (Ritsumeikan Univ.), Akihisa Yamada (SHARP)
p. 31
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.