Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2007-7
Automatic Generation of a Verification Environment for Hardware Units
-- Application to a Bus Bridge Design --
Rafael Kazumiti Morizawa, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Labs.)
pp. 1 - 6
VLD2007-8
On a lower bound for DAG covering problem and its application to an exact algorithm
Yusuke Matsunaga (Kyushu Univ.)
pp. 7 - 12
VLD2007-9
A Clock Deskew Method using PDE with Discrete Delay
Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC)
pp. 13 - 18
VLD2007-10
An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA
Masayuki Hiromoto, Atsuko Takahashi, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.)
pp. 19 - 24
VLD2007-11
An SIMD MSD Multiplier based on variable GF($2^m$) for Elliptic Curve Cryptosystem
Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 25 - 29
VLD2007-12
On power-conscious approach for prefix graph synthesis
Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.)
pp. 31 - 36
VLD2007-13
A Flexible Power and Task Modeling for LSI Blocks
Tatsuya Koyagi, Masahiro Fukui (Ritsumeikan Univ.), Resve Saleh (Univ. of British Columbia)
pp. 37 - 42
VLD2007-14
A fast maximum delay estimation method for specified yield by statistical static timing analysis.
Hiroki Furuya, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech)
pp. 43 - 47
VLD2007-15
An algorithm of power grid optimization for high-level floorplan
Takayuki Hayashi, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ.)
pp. 49 - 54
VLD2007-16
Effect of Dummy Fill on High-Frequency Characteristics of On-Chip Interconnects
Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.)
pp. 55 - 59
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.