IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2008-01-16 / Issue Date : 2008-01-09

VLD2007-105
[Invited Talk] Flex Power FPGA
Hanpei Koike (AIST)
pp. 1 - 6

VLD2007-106
High speed control system using Multilevel control circuit
Hiroaki Maekawa, Ryuichi Tanaka, Masatoshi Sekine (TUAT)
pp. 7 - 12

VLD2007-107
Scalable RHPC(Reconfigurable HPC) by using FPGA array
Hiroaki Iijima, Kazuki Sato, Masatoshi Sekine (Tokyo Univ. of Agriculture and Technology)
pp. 13 - 18

VLD2007-108
Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs
Yuzo Nishioka, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 19 - 24

VLD2007-109
An optimization method of DMA transfer for the SRC-6 reconfigurable machine
Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 25 - 30

VLD2007-110
A study of the effectiveness of dynamic partial reconfiguration for size and power reduction
Yohei Hori, Hirofumi Sakane, Kenji Toda (AIST)
pp. 31 - 36

VLD2007-111
Development of verification and power estimation methodology for circuits with Run Time Power Gating
Mitsutaka Nakata, Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Kimiyoshi Usami (S.I.T.), Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.)
pp. 37 - 42

VLD2007-112
Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating
Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Mitsutaka Nakata, Kimiyoshi Usami (S.I.T.), Yohei Hasegawa, Naomi Seki, Hideharu Amano (Keio Univ.)
pp. 43 - 48

VLD2007-113
An efficient algorithm for RTL power macro modeling and library building
Masaaki Ohtsuki, Masato Kawai, Tatsuya Koyagi, Masahiro Fukui (Ritsumeikan Univ.)
pp. 49 - 54

VLD2007-114
Solving the Quadratic Assignment Problem by Hardware Based on a Systolic Algorithm
Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.)
pp. 55 - 60

VLD2007-115
A Regular Expression String Matching Machine Allowing Pattern Setting During Execution Time and Its FPGA Implementation
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.)
pp. 61 - 66

VLD2007-116
Fast solution method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2
Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex)
pp. 67 - 72

VLD2007-117
A Method of Design and Update for an Address Generator Using a Hybrid Method
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (K.I.T.)
pp. 73 - 78

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan