IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 107, Number 415

VLSI Design Technologies

Workshop Date : 2008-01-17 / Issue Date : 2008-01-10

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Table of contents

VLD2007-118
[Invited Talk] ICCAD summary report
Yusuke Matsunaga (Kyushu Univ.)
pp. 1 - 6

VLD2007-119
A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures
Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 7 - 12

VLD2007-120
Scheduling and Memory Binding in High Level Synthesis for FPGAs
Yuki Sagawa, Tsuyoshi Sadakata, Yusuke Matsunaga (Kyusyu Univ.)
pp. 13 - 18

VLD2007-121
Improvement in data communication between PEs for SIMD type processor MX core
Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ)
pp. 19 - 24

VLD2007-122
Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation
Takahiro Kawahara, Shinobu Miwa, Hajime Shimada (Kyoto Univ.), Shin-ichiro Mori (Univ. of Fukui), Shinji Tomita (Kyoto Univ.)
pp. 25 - 30

VLD2007-123
Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication
Shotaro Saito, Yasufumi Sugimori, Yoshinori Kohama, Tadahiro Kuroda, Yohei Hasegawa, Hideharu Amano (Keio Univ.)
pp. 31 - 36

VLD2007-124
An effective data I/O mechanism utilizing FIFOs for an array processor
Yuusuke Nomoto, Yuka Sato, Toshiaki Miyazaki (Univ. of Aizu)
pp. 37 - 42

VLD2007-125
Analysis of retention time under continuous reconfiguration of a DORGA
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
pp. 43 - 47

VLD2007-126
A fast optical reconfiguration experiment of a dynamic optically reconfigurable gate array
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
pp. 49 - 52

VLD2007-127
Fault tolerance analysis for holographic memories in optically reconfigurable gate arrays.
Kouji Shinohara, Minoru Watanabe (Shizuoka Univ.)
pp. 53 - 57

VLD2007-128
A Tile Based Dynamically Reconfigurable Architecture with Dual ALU-array/RISC Processor Operating Mode Capability
Shin'ichi Kouyama, Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.)
pp. 59 - 64

VLD2007-129
Functionally-partitioned JPEG decoder for partial dynamic reconfiguration
Taiichiro Yatsunami, Hideaki Yoshihiro, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 65 - 70

VLD2007-130
A Method for Saving and Restoring Context Data of Hardware Tasks on the Dynamically Reconfigurable Processor
Vu Manh Tuan, Hideharu Amano (Keio Univ.)
pp. 71 - 76

VLD2007-131
An L1 Data Cache Optimization Algorithm for Application Processor Cores
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 77 - 82

VLD2007-132
A Processor Kernel Generation Method for Application Processors
Toshihiro Hiura, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 83 - 88

VLD2007-133
A Hybrid Design Space Exploration Approach for a Coarse-Grained Reconfigurable Accelerator
Farhad Mehdipour (Kyushu Univ.), Hamid Noori (ISIT), Hiroaki Honda, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
pp. 89 - 94

VLD2007-134
VLIW Extension of Software Development Environment Construction Tool ArchC
Takanori Morimoto (Kwansei Gakuin Univ.), Takahiro Kumura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.)
pp. 95 - 100

VLD2007-135
Hardware Consious Style: a C Language Style for Hardware Design
Kaiyi Mao, Hideharu Amano, Satoshi Tsutsumi, Vasutan Tunbunheng (Keio Univ.)
pp. 101 - 106

VLD2007-136
C to HDL compiler for rapid HW-SW co-simulation models
Yasuhiro Ito, Yutaka Sugawara, Kei Hiraki (Tokyo Univ.)
pp. 107 - 112

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan