IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2008-03-07 / Issue Date : 2008-02-29

VLD2007-156
A delay balancing technique for wave-pipelining
Keiichiro Sano, Jubee Tada (Yamagata Univ), Ryusuke Egawa (Touhoku Univ), Gensuke Goto (Yamagata Univ)
pp. 1 - 6

VLD2007-157
Enhancing Multimedia Processing by Wave-Pipelining a Multifunctional Execution Unit
Kazunori Noda, Atuko Yokoyama, Hiroki Takeda, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.)
pp. 7 - 12

VLD2007-158
A Self-timed Processor with Dynamic Voltage Scaling
Taku Sogabe, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo)
pp. 13 - 18

VLD2007-159
A High-Throughput Architectures for LDPC Coded OFDM Baseband Processor
Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.)
pp. 19 - 24

VLD2007-160
Design of High-rate Irregular LDPC Decoder based on Accelerated Message-passing Schedule
Yuta Abe, Naoki Tajima, Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)
pp. 25 - 30

VLD2007-161
The Improvement of the Ubiqitus Processor HCgorilla
Hiroki Takeda, Kazunori Noda, Atuko Yokoyama, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ)
pp. 31 - 36

VLD2007-162
An adaptive error concealment order H.264/AVC
Jun Wang, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)
pp. 37 - 40

VLD2007-163
A Low-cost Speed and Yield Enhancement Method Using Embedded Delay Detectors on FPGAs
Yohei Kume, Yuuri Sugihara, Ngo Cam Lai, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
pp. 41 - 46

VLD2007-164
Application-Oriented Dynamic Reconfigurable Network Processor Architecture and Its Optimization Method
Motonori Ohta, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ)
pp. 47 - 52

VLD2007-165
Implementation and Evaluation of Network Security using An Embedded Programmable Logic Matrix (ePLX)
Mitsutaka Matsumoto, Shun Kimura (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology Corp.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.)
pp. 53 - 58

VLD2007-166
An Object Oriented System LSI Design Methodology and Its Evaluation
Takafumi Kohara, Hiroyuki Terai, Seigo Masuoka (Kinki University), Akihisa Yamada (SHARP Corp.), Takashi Kambe (Kinki University)
pp. 59 - 64

VLD2007-167
A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor
Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University)
pp. 65 - 68

VLD2007-168
New technology of independent-gate controlled Double-Gate transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 69 - 74

VLD2007-169
New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 75 - 80

VLD2007-170
Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 81 - 86

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan