Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
RECONF2009-1
Performance Evaluation of Reconfigurable Processor Hy-DiSC based on MeP Hardware Extension
Ken'ichi Umeda, Takuro Uchida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ)
pp. 1 - 6
RECONF2009-2
Real Chip Evaluation of Dynamically Reconfigurable Processor Array MuCCRA-3
Yoshihiro Yasuda, Yoshiki Saito, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.)
pp. 7 - 12
RECONF2009-3
Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs
Sen In, Hiroki Matsutani, Daihang Wang (Keio Univ), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ)
pp. 13 - 18
RECONF2009-4
A Power of FPGA Reduction Using FPGA Routing Structure Based on the Small-World Network
Shoichi Nishida (Kumamoto Univ.), Yuzo Nishioka (Hitachi-Omron Terminal Solutions, Corp.), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 19 - 24
RECONF2009-5
Proposal and Implementation of High Throughput Algorithm for Combination Generation
Akira Tsuji, Norio Yamagaki, Satoshi Kamiya (NEC)
pp. 25 - 30
RECONF2009-6
Accelerating HMMER search using FPGA
Toyokazu Takagi, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 31 - 36
RECONF2009-7
Performance evaluation of an auto-generation algorithm of hardware modules for an FPGA-based general-purpose biochemical simulator
Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata (Nagasaki Univ), Yasunori Osana (Seikei Univ), Masato Yoshimi (Doshisha Univ), Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi (Keio Univ), Kiyoshi Oguri (Nagasaki Univ)
pp. 37 - 42
RECONF2009-8
[Invited Talk]
Development of Interactive Supercomputing Environment
Shin-ichiro Mori (Univ. of Fukui), Tomohiro Kuroda, Naoto Kume (Kyoto Univ.), Yoshihiro Kuroda (Osaka Univ.), Megumi Nakao, Hajime Shimada, Yasuhiko Nakashima (NAIST), Shinji Tomita (Kyoto Univ.)
pp. 43 - 48
RECONF2009-9
Recovery and syncronization technique for TMR softcore processor
Yoshihiro Ichinomiya, Shiro Tanoue, Toshio Yabuta, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 49 - 54
RECONF2009-10
A low-power clustering tool using both routability and activity for FPGAs
Junya Eto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 55 - 60
RECONF2009-11
A Memory Access Optimization Method for Reconfigurable Systems Based on a Multithread Programming Model
Keisuke Dohi, Sayaka Shida, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ.)
pp. 61 - 66
RECONF2009-12
Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis
Yohei Hori, Mai Itoh (Chuo Univ.), Hideki Imai (Chuo Univ./AIST)
pp. 67 - 72
RECONF2009-13
*
Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.)
pp. 73 - 78
RECONF2009-14
Real-time processing of local contrast enhancement on FPGA
Kentaro Kokufuta, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 79 - 84
RECONF2009-15
Performance comparison of GPU and FPGA in image processing
Shuichi Asano, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 85 - 90
RECONF2009-16
A comparative study of implementing N-body simulation on FPGAs, GPUs and general purpose processors
Tsuyoshi Hamada (Nagasaki Univ), Khaled Benkrid (Univ. of Edinburgh), Kiego Nitadori (RIKEN), Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ)
pp. 91 - 96
RECONF2009-17
Modularizing Flux Limiter Functions in UPACS for CFD Accelerator FLOPS-2D
Kenta Inakagata, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)
pp. 97 - 102
RECONF2009-18
Acceleration of UPACS subroutines with FPGAs
Takaaki Yokoyama, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)
pp. 103 - 108
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.