IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 109, Number 320

Reconfigurable Systems

Workshop Date : 2009-12-03 - 2009-12-04 / Issue Date : 2009-11-26

[PREV] [NEXT]

[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]

[PROGRAM] [BULK PDF DOWNLOAD]


Table of contents

RECONF2009-41
A Case Study of Error Correction Technique for SRAM-based FPGA using the Partial Reconfiguration
Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 1 - 6

RECONF2009-42
An inversion/non-inversion dynamic optical reconfiguration architecture using a MEMS
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
pp. 7 - 12

RECONF2009-43
Optical buffering technique under space radiation environment
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
pp. 13 - 18

RECONF2009-44
Evaluation of circuit proliferation method that uses concept of pressure in PCA
Yuta Araki, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ.)
pp. 19 - 24

RECONF2009-45
A Virus Scanning Engine Using a Parallel Sieve Method and the MPU
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.)
pp. 25 - 30

RECONF2009-46
Development of Standard Evaluation Environment for Side-channel Attacks and Countermeasures
Toshihiro Katashita (AIST), Yohei Hori (Chuo Univ.), Akashi Satoh (AIST)
pp. 31 - 36

RECONF2009-47
Evaluation of CryptMT steam cipher implemented on FPGA
Naoko Yamada (Keio Univ.), Atsunori Sakurai, Keisuke Iwai, Takakazu Kurokawa (National Defense Academy), Hideharu Amano (Keio Univ.)
pp. 37 - 42

RECONF2009-48
"FLOPS2D" Design Concept -- Floating Point Custom Computer for CFD --
Naoyuki Fujita (JAXA)
pp. 43 - 48

RECONF2009-49
A Study of two input LUT array type programmable logic architecture for cryptographic processing
Ai Nakanishi, Kouta Ishibashi, Yuuichirou Kurokawa, Takeshi Fujino (Ritsumeikan Univ.)
pp. 49 - 54

RECONF2009-50
Selection Technique of Pipeline Parameters for FLOPS-2D:Multi-FPGA System Environment
Hirokazu Morishita, Kenta Inakagata (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)
pp. 55 - 60

RECONF2009-51
[Invited Talk] A Project on Dynamically Reconfigurable Processors: MuCCRA -- Design emvironment, Low Power design and 3D wireless interconnect --
Hideharu Amano (Keio Univ.)
pp. 61 - 66

RECONF2009-52
An Optimal Algorithm for 3-adress QDD Machine Code
Taisuke Fukuyama, Tsutomu Sasao, Munehiro Matsuura (Kyusyu Inst. of Tech.)
pp. 67 - 72

RECONF2009-53
Implementation of core functions of a H264 encoder on STP-engine
Yoshihiro Takamatsu, Takao Toi, Hideharu Amano (Keio Univ.)
pp. 73 - 78

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan