IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 110, Number 210

VLSI Design Technologies

Workshop Date : 2010-09-27 - 2010-09-28 / Issue Date : 2010-09-20

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Table of contents

VLD2010-42
Ordered Coloring for Skew Adjustability-Aware Resource Binding
Mineo Kaneko (JAIST)
pp. 1 - 6

VLD2010-43
Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors
Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Michitaka Kameyama (Tohoku Univ.)
pp. 7 - 12

VLD2010-44
Design and Evaluation of Arbiter Physical Unclonable Functions
Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino (Ritsumeikan Univ.)
pp. 13 - 18

VLD2010-45
[Invited Talk] Analog Circuit Optimization Using Pareto-Optimality
Yu Liu, Masato Yoshioka, Katsumi Homma, Yuzi Kanazawa (Fujitsu Labs), Toshiyuki Shibuya (Fujitsu Labs of America)
pp. 19 - 24

VLD2010-46
[Invited Talk] An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit
Satoshi Komatsu, Mohamed Abbas (Univ. of Tokyo), Yasuo Furukawa (Advantest), Kunihiro Asada (Univ. of Tokyo)
pp. 25 - 30

VLD2010-47
[Invited Talk] Length Matching Routing on Single Layer for PCB Routing Design
Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.)
pp. 31 - 36

VLD2010-48
A Method of Analog IC Placement with Common Centroid Constraints
Keitaro Ue, Kunihiro Fujiyoshi (TUAT)
pp. 37 - 42

VLD2010-49
Analog Layout Retargeting with Constraint Extraction by Matching of Fundamental Circuit Components and Layout Regularity
Kazuhiko Shibata, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 43 - 48

VLD2010-50
Regularity-Oriented Compaction with Z-cut Perturbation
Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 49 - 54

VLD2010-51
Fast Optimization on Minimum Perturbation Placement Realization
Yuki Kouno, Yasuhiro Takashima (Univ. of Kitakyushu), Atsushi Takahashi (Osaka Univ.)
pp. 55 - 60

VLD2010-52
[Invited Talk] Application of Ultra Low-power Circuit Techniques to Wireless Terminals in Wide Area Ubiquitous Network -- Approach to Nano-watt Wireless Sensor Nodes --
Yuichi Kado (Kyoto Inst. of Tech.), Mitsuru Harada, Mamoru Ugajin, Akihiro Yamagishi, Mitsuo Nakamura (NTT)
pp. 61 - 66

VLD2010-53
A study of temperature characteristics of ring-oscillator based threshold voltage estimation
Takumi Uezono, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.)
pp. 67 - 70

VLD2010-54
Analysis and Evaluation of Simultaneous Switching Noise of FPGA
Yo Takahashi, Toshio Sudo (SIT), Kunio Ota, Kazuhisa Matsuge (Toshiba)
pp. 71 - 76

VLD2010-55
Measurement Circuits for Acquiring SET PulseWidth Distribution with Fine Time Resolution
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
pp. 77 - 82

VLD2010-56
Modeling of Latching Probability of Soft-Error-Induced Pulse
Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.)
pp. 83 - 88

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan