Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2012-1
An Acceleration of a Graph Cut Segmentation with FPGA
Daichi Kobori, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 1 - 6
RECONF2012-2
An Imaging Device Control System
Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba)
pp. 7 - 12
RECONF2012-3
FPGA implementation of a video-based real-time pupil detection method
Yuma Hatanaka, Keisuke Dohi, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki City Univ)
pp. 13 - 18
RECONF2012-4
A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array
Toru Katagiri, Kazuei Hironaka, Hideharu Amano (Keio Univ.)
pp. 19 - 24
RECONF2012-5
Development of a demonstration system for Ultra-low-power FPGA with Fine-Grained Field-Programmable Threshold Voltage Control
Takashi Kawanami (KIT), Masakazu Hioki (AIST), Yohei Matsumoto (Kaiyo Univ.), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)
pp. 25 - 30
RECONF2012-6
Optimization of PE Array Interconnection on CMA to Reduce Configuration Data
Rie Uno (keio Univ.), Nobuaki Ozaki, Hideharu Amano (Keio Univ.)
pp. 31 - 36
RECONF2012-7
Implementation and Evaluation of FPGA-based Data Compression Hardware of Floating-Point Data-Stream
Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 37 - 42
RECONF2012-8
An FPGA Implementation for a 3-layer Perceptron with the FDFM Processor Core Approach
Yuki Agou, Yasuaki Ito, Koji Nakano (Hiroshima Univ.)
pp. 43 - 48
RECONF2012-9
Implementation of Square Root Calculator on Reconfigurable Processor DS-HIE
Takashi Ueda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 49 - 54
RECONF2012-10
Scalability Analysis of Tightly-Coupled FPGA-Cluster for Lattice Boltzmann Computation
Yoshiaki Kono, Kentaro Sano, Ryotaro Chiba, Satoru Yamamoto (Tohoku Univ.)
pp. 55 - 60
RECONF2012-11
Hard error avoidance for TMR module using dynamic relocation in an FPGA
Hiroki Tanaka, Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 61 - 66
RECONF2012-12
a design of an interconnection system of modules and a control unit of reconfiguration for embedded systems utilizing dynamic reconfiguration
Tomokazu Mizuno, Yoshiaki Kida, Ryo Kamide, Shin Terada, Mitsuyoshi Tokuda, Tomonori Izumi (Ritsumeikan Univ.)
pp. 67 - 70
RECONF2012-13
An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects
Yuuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 71 - 76
RECONF2012-14
Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis
Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ)
pp. 77 - 82
RECONF2012-15
Implementation of delay control methods for FPGA-based digital DC-DC Converters
Yoshihiko Yamabe, Kanako Nakashima, Keisuke Dohi, Kazuma Hamawaki, Kentaro Yamashita, Kazuhiro Kajiwara, Fujio Kurokawa, Yuichiro Shibata, Kiyoshi Oguri (Univ.)
pp. 83 - 88
RECONF2012-16
Development of Application for Heterogeneous Multi-Core Processor
Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.)
pp. 89 - 94
RECONF2012-17
AN FPGA ACCELERATION OF A LEVEL SET SEGMENTATION METHOD
Haruhisa Tsuyama, Tsutomu Maruyama (Tsukuba Univ.)
pp. 95 - 100
RECONF2012-18
Proposal and Evaluation of photon mapping acceleration using FPGA
Takuya Kuhara, Masato Yoshimi, Mitsunori Miki (Doshisha Univ.)
pp. 101 - 106
RECONF2012-19
Real-time Corner and Polygon Detection System on FPGA
Chunmeng Bi, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 107 - 112
RECONF2012-20
SOM-based FPGA Placement Method using Shimbel Index
Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 113 - 118
RECONF2012-21
A Study of HW/SW Co-design with JavaRock
Takefumi Miyoshi, Satoshi Funada (e-trees)
pp. 119 - 124
RECONF2012-22
A Domain Specific Language and Toolchain for Runtime Binary Acceleration
Takaaki Miyajima (Keio Univ.), David Thomas (Imperial), Hideharu Amano (Keio Univ.)
pp. 125 - 130
RECONF2012-23
A Hardware Implementation and an FPGA Prototyping of a Connect-6 Player Algorithm Using Impulse-C
Naohisa Arakawa, Tomonori Izumi (Ritsumeikan Univ.)
pp. 131 - 136
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.