IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 113, Number 451

Silicon Device and Materials

Workshop Date : 2014-02-28 / Issue Date : 2014-02-21

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Table of contents

SDM2013-165
[Invited Talk] Large-Radius Neutral Beam Enhanced Chemical Vapor Deposition Process for Non-Porous Ultra-low-k SiOCH
Yoshiyuki Kikuchi (Tokyo Electron/Tohoku Univ.), Seiji Samukawa (Tohoku Univ.)
pp. 1 - 5

SDM2013-166
[Invited Talk] Trend of practical technology in advanced low-k integration
Naoya Inoue (Renesas Electronics Corp.)
pp. 7 - 12

SDM2013-167
[Invited Talk] Impact of Back Grind Damage on Si Wafer Thinning for 3D Integration
Yoriko Mizushima (Fujitsu Lab./Tokyo Inst. of Tech.), Youngsuk Kim (Tokyo Inst. of Tech./Disco), Tomoji Nakamura (Fujitsu Lab.), Ryuichi Sugie, Hideki Hashimoto (Toray Research Center), Akira Uedono (Univ. of Tsukuba), Takayuki Ohba (Tokyo Inst. of Tech.)
pp. 13 - 18

SDM2013-168
[Invited Talk] Injection technique of organic-base conductive ink toward fast formation of TSV
Jin Kawakita (National Institute for Materials Science)
pp. 19 - 21

SDM2013-169
[Keynote Address] Integrated Circuits in Future -- How do we find opportunity and challenge of integrated circuits? --
Kazuya Masu (Tokyo Inst. of Tech.)
pp. 23 - 28

SDM2013-170
[Invited Talk] Novel Implantation Process of Carbon Nanotubes for Plugs and Vias, and their Integration with Transferred Multilayer Graphene Wire Obtained by Annealing Sputtered Amorphous Carbon
Motonobu Sato, Makoto Takahashi, Mizuhisa Nihei, Shintaro Sato, Naoki Yokoyama (AIST)
pp. 29 - 33

SDM2013-171
[Invited Talk] Low temperature growth of dense carbon nanotube arrays on conductive underlayers
Suguru Noda (Waseda Univ.), Nuri Na (Waseda Univ./Univ. of Tokyo), Takashi Shirai, Keisuke Nomura (Univ. of Tokyo), Kei Hasegawa (Waseda Univ.)
pp. 35 - 38

SDM2013-172
[Invited Talk] TSV Liner Formation with Vapor Deposited Polyimides
Takafumi Fukushima, Mariappan Murugesan, Jicheol Bea, Kangwook Lee, Mitsumasa Koyanagi (Tohoku Univ.)
pp. 39 - 42

SDM2013-173
[Invited Talk] 15μm-pitch Bump Interconnections Relied on Flip-chip Bonding Technique -- for Advanced Chip Stacking Applications --
Masahiro Aoyagi, Thanh-Tung Bui, Fumiki Kato, Naoya Watanabe, Shunsuke Nemoto, Katsuya Kikuchi (AIST)
pp. 43 - 46

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan