IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 118, Number 334

VLSI Design Technologies

Workshop Date : 2018-12-05 - 2018-12-07 / Issue Date : 2018-11-28

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Table of contents

VLD2018-40
Design Automation and Optimal Architecture of NLoC
Yuto Umeda, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 1 - 6

VLD2018-41
A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones
Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 7 - 11

VLD2018-42
Prototyping of Real-time Computer-Aided Diagnosis System for Colorectal Endoscopic Movies and Images with Machine Learning
Takumi Okamoto, Masayuki Odagawa, Koujiroh Takebayashi, Mikihisa Nagano, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (JR Hiroshima Hospital), Shinji Tanaka (Hiroshima Univ.), Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba (Cadence, Japan)
pp. 13 - 18

VLD2018-43
[Keynote Address]
Hiroki Nakahara (Titech)
p. 29

VLD2018-44
Basic Evaluation of Netlist Function Inference using GCN
Hiroki Oyama, Motoki Amagasaki, Masahiro Iida (kumamoto Univ.), Hiroaki Yasuda, Hiroto Ito (MITSUBISHI ELECTRIC ENGINEERING)
pp. 31 - 36

VLD2018-45
Improved Routing Method for Two Layer Self-Aligned Double Patterning
Shoya Tamura, Kunihiro Fujiyoshi (TUAT)
pp. 37 - 42

VLD2018-46
Horizontal Wireless Bus for Free-Form SiP
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai (The Univ. of Tokyo)
pp. 43 - 48

VLD2018-47
Stochastic Number Generation Considering Trade-off between Error and Overhead
Yudai Sakamoto, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 65 - 70

VLD2018-48
Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD
Hidehito Fujiishi, Tokio Kamada, Tetsuo Hironaka, Kazuya Tanigawa, Atsushi Kubota (Hiroshima city Univ.)
pp. 71 - 76

VLD2018-49
Secure PUF Authentication Method against Machine Learning Attack
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
pp. 77 - 82

VLD2018-50
(See Japanese page.)
pp. 83 - 88

VLD2018-51
On the Generation of Random Capture Safe Test Vectors Using Neural Networks
Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.)
pp. 89 - 94

VLD2018-52

Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 95 - 100

VLD2018-53
A Case Study on Memory Architecture Exploration for FPGA-based Manycores
Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 101 - 106

VLD2018-54
Improved Thread Execution for GPU-oriented OpenCL Programs on Multicore Processors
Takafumi Miyazaki, Hayato Hidari, Naohisa Hojo (Ritsumeikan Univ), Naohisa Hojo (Osaka Univ), Hiroyuki Tomiyama (Ritsumeikan Univ)
pp. 107 - 111

VLD2018-55
An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura (NTT), Koji Yamazaki (NTT-AT), Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT)
pp. 113 - 118

VLD2018-56
Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 119 - 124

VLD2018-57
Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips
Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT)
pp. 125 - 130

VLD2018-58
Study on the Applicability of ATPG Pattern for DFT Circuit
Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 131 - 136

VLD2018-59
Register-Transfer Level Exploration of Segments Utilizable for Scan Path Synthesis
Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 137 - 142

VLD2018-60
An efficient SAT-attack algorithm against logic encryption
Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
pp. 143 - 148

VLD2018-61
A Hybrid Method Using Monte-Carlo Tree Search and Gibbs Sampling Method for Solving Motif Extraction Problems
Yusuke Yuasa, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (HCU)
pp. 149 - 154

VLD2018-62

Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima (NAIST)
pp. 155 - 160

VLD2018-63
Malleable Task Scheduling for Energy Minimization on Heterogeneous Multicores
Hiroki Nishikawa, Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 171 - 176

VLD2018-64
Communication-Aware Scheduling for Data-Parallel Tasks
Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 177 - 182

VLD2018-65
Design and fabrication of characteristics measurement circuit for CMOS-compatible ultra-low-power non-volatile memory element using FiCC
Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
pp. 183 - 188

VLD2018-66
Flip-Flops with different retention characteristics for process variation estimation
Kento Fukazawa, Shinichi Nishizawa, Kazuhito Ito (Saitama Univ.)
pp. 189 - 193

VLD2018-67
A study on estimating the degradation of critical path delay using replica sensors
Kunihiro Oshima, Son Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)
pp. 195 - 200

VLD2018-68
[Keynote Address] AI in medical imaging diagnosis
Hiroshi Fujita (Gifu Univ.)
p. 201

VLD2018-69
A Radiation-hard Low-delay Flip-Flop with Stacking Structure for SOI Process
Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
pp. 203 - 208

VLD2018-70
Process Variation-aware Model-based OPC using 0-1 Quadratic Programming
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC)
pp. 209 - 214

VLD2018-71
Comparison of Machine Learning-Based Lithography Hotspot Detection Methods under Optimized Hyperparameters
Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 215 - 220

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan