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Technical Committee on Component Parts and Materials (CPM) (Searched in: 2009)
Search Results: Keywords 'from:2009-12-02 to:2009-12-02'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 10:20 |
Kochi | Kochi City Culture-Plaza | A Circuit Design Method based on Foreknown Regularity between I/O Jin Sato, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.)  CPM2009-134 ICD2009-63 |
The paper proposes a method of designing an arithmetic unit based on the regularity of the output depending on input pat... [more] | CPM2009-134 ICD2009-63 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 10:40 |
Kochi | Kochi City Culture-Plaza | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) CPM2009-135 ICD2009-64 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | CPM2009-135 ICD2009-64 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 11:00 |
Kochi | Kochi City Culture-Plaza | A WiMAX Turbo Decoder with Tailbiting BIP Architecture Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku Univ.), Hisanori Fujisawa (Fujitsu Laboratories Ltd.), Takashi Ito (Tohoku Univ.) CPM2009-136 ICD2009-65 |
In this paper, a tailbiting block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy e... [more] | CPM2009-136 ICD2009-65 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 11:20 |
Kochi | Kochi City Culture-Plaza | A Reference CMOS Circuit Structure for Evaluation of Power Supply Noise Tetsuro Matsuno, Daisuke Kosaka (Kobe Univ.), Makoto Nagata (Kobe Univ./ CREST-JST) CPM2009-137 ICD2009-66 |
Accurate understandings of dynamic noises in power delivery networks of very large scale integration (VLSI) chips are st... [more] | CPM2009-137 ICD2009-66 pp.19-22 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 13:15 |
Kochi | Kochi City Culture-Plaza | [Invited Talk]
PI/SI/EMI for Chip/Package/Board Co-Design Hideki Asai (Shizuoka Univ.) CPM2009-138 ICD2009-67 |
[more] | CPM2009-138 ICD2009-67 pp.23-27 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 13:50 |
Kochi | Kochi City Culture-Plaza | [Invited Talk]
Failures due to Terrestriall Neutrons in Most Advanced Semicondutor Devices
-- Impacts and Hardening Techniques down to 22nm Design Rule -- Eishi Ibe, Kenichi Shimbo, Hitoshi Taniguchi, Tadanobu Toba (Hitachi, Ltd.) CPM2009-139 ICD2009-68 |
The status-of-the-art in failures and their mechanisms of CMOS memories and logic gates induced by terrestrial neutrons ... [more] | CPM2009-139 ICD2009-68 pp.29-34 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 14:25 |
Kochi | Kochi City Culture-Plaza | [Invited Talk]
Noise characteristics improvement of an LSI by using an interposer embedded capacitors Yoshiyuki Saito, Eiji Takahashi, Chie Sasaki (Panasonic), Yasuhiro Sugaya (Panasonic Electronic Devices) CPM2009-140 ICD2009-69 |
[more] | CPM2009-140 ICD2009-69 pp.35-39 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 15:15 |
Kochi | Kochi City Culture-Plaza | [Invited Talk]
EMC jisso Design at GHz frequencies Takashi Harada, Naoki Kobayashi, Ken Morishita, Hisashi Ishida (NEC Corp.) CPM2009-141 ICD2009-70 |
[more] | CPM2009-141 ICD2009-70 pp.41-46 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 16:00 |
Kochi | Kochi City Culture-Plaza | [Panel Discussion]
EMC Circuit Design and Jisso Design for System LSI
-- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side -- Hideki Osaka (HITACHI Ltd.), Hideki Asai (Shizuoka Univ.), Hidefumi Ibe (HITACHI Ltd.), Yoshiyuki Saito (Panasonic), Takashi Harada (NEC), Narimasa Takahashi (IBM Japan) CPM2009-142 ICD2009-71 |
Nowadays, a JISSO design is very important to get the target performance out of a system LSI. More specifically, co-desi... [more] | CPM2009-142 ICD2009-71 pp.47-49 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 14:05 |
Kochi | Kochi City Culture-Plaza | Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST) VLD2009-43 DC2009-30 |
In high-level synthesis of LSI, it is an important task to minimize the number of connections between modules (functiona... [more] | VLD2009-43 DC2009-30 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 14:25 |
Kochi | Kochi City Culture-Plaza | A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System Kazuhito Ito, HyunJoon Kim (Saitama Univ.) VLD2009-44 DC2009-31 |
In processing with conditional operations, computations are executed conditionally based on the result of condition ope... [more] |
VLD2009-44 DC2009-31 pp.19-24 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 14:45 |
Kochi | Kochi City Culture-Plaza | A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI Hidekazu Seto, Kazuhito Ito (Saitama Univ.) VLD2009-45 DC2009-32 |
The energy dissipation by data communications on a LSI chip depends on the layout of modules as well as how data are com... [more] | VLD2009-45 DC2009-32 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 15:20 |
Kochi | Kochi City Culture-Plaza | Evaluation of Hardware/Software Partitioning Method with Consideration of Timing Junya Matsunaga, Michiaki Muraoka (Kochi Univ.) VLD2009-46 DC2009-33 |
The optimal hardware/software partitioning is an important issue in the system level design. In the conventional design,... [more] | VLD2009-46 DC2009-33 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 15:40 |
Kochi | Kochi City Culture-Plaza | Two-level Cache Simulation with L2 Unified Cache for Embedded Applications Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-47 DC2009-34 |
In this paper, we propose a two-level cache simulation method with L2 unified cache for embedded applications. It simula... [more] | VLD2009-47 DC2009-34 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 16:00 |
Kochi | Kochi City Culture-Plaza | Simulation-Based Bus Width Optimization for Two-Level Cache Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-48 DC2009-35 |
In this paper, we propose a simulation-based bus width and cache configuration optimization approach for two-level cache... [more] | VLD2009-48 DC2009-35 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 10:00 |
Kochi | Kochi City Culture-Plaza | Correlation of Mitigation of Soft-error Rate of Routers between Neutron Irradiation Test and Field Soft-error Data Kenichi Shimbo, Tadanobu Toba, Hidehumi Ibe, Koji Nishii (Hitachi) CPM2009-143 ICD2009-72 |
We evaluated the soft error tolerance of the information system by the neutron irradiation test. We estimated the correl... [more] | CPM2009-143 ICD2009-72 pp.51-55 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 10:20 |
Kochi | Kochi City Culture-Plaza | A Target Imedance of Power Distribution Network and LSI Packaging Design Narimasa Takahashi, Yoshiyuki Kosaka, Masatoshi Ishii (IBM Japan), Makoto Shiroshita (KYOCERA SLC) CPM2009-144 ICD2009-73 |
This paper describes the modeling analysis for a power distribution network and demonstrate co-design and co-simulation... [more] | CPM2009-144 ICD2009-73 pp.57-62 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 10:40 |
Kochi | Kochi City Culture-Plaza | Evaluation of Waveform-Improvement performance on the Segmental Transmission Line Yuki Shimauchi, Hiroshi Nakayama, Yoshiki Yamaguchi, Noriyuki Aibe (Tsukuba Univ.), Ikuo Yoshihara (Miyazaki Univ.), Moritoshi Yasunaga (Tsukuba Univ.) CPM2009-145 ICD2009-74 |
As processor-speed increases, high-speed signal-propagation in the PCB traces following the processor-speed is also requ... [more] | CPM2009-145 ICD2009-74 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 11:00 |
Kochi | Kochi City Culture-Plaza | [Invited Talk]
Study on the Signal Integrity Design of a High-Speed LSI and a Printed Circuit Board Seiichi Saito, Keitaro Yamagishi (Mitsubishi Electric) CPM2009-146 ICD2009-75 |
This paper describes the signal integrity design focusing on the signal reflection which should be considered in design ... [more] | CPM2009-146 ICD2009-75 pp.69-74 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 10:00 |
Kochi | Kochi City Culture-Plaza | An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2009-49 DC2009-36 |
Soft error tolerance evaluation method is necessary for the soft error aware logic design. An evaluation method with Mar... [more] | VLD2009-49 DC2009-36 pp.55-60 |
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