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| Chair |
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Akira Onozawa (NTT) |
| Vice Chair |
|
Kimiyoshi Usami (Shibaura Inst. of Tech.) |
| Secretary |
|
Akihisa Yamada (Sharp), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) |
|
| Conference Date |
Wed, Mar 2, 2011 13:10 - 18:00
Thu, Mar 3, 2011 09:55 - 16:55
Fri, Mar 4, 2011 10:00 - 16:20 |
| Topics |
Design Technology for System-on-Silicon |
| Conference Place |
|
| Address |
3-11-1 Nishi, Naha-shi, Okinawa, Japan |
| Transportation Guide |
http://www.tiruru.or.jp/?page_id=31 |
Contact
Person |
Prof. Katsuhiko Shimabukuro
+81-98-895-8694 |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Wed, Mar 2 PM
13:10 - 14:50 |
| (1) |
13:10-13:35 |
An Architecture Exploration Method based on a Branch-and-Bound Strategy for Embedded VLIW Processors  VLD2010-116 |
Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) |
| (2) |
13:35-14:00 |
Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions VLD2010-117 |
Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) |
| (3) |
14:00-14:25 |
Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems VLD2010-118 |
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) |
| (4) |
14:25-14:50 |
Intra-task Analysis of Worst Case Execution Time and Average Energy Consumption on DEPS Framework VLD2010-119 |
Hirotaka Kawashima, Gang Zeng, Noritoshi Atsumi, Tomohiro Tatematsu, Hiroaki Takada (Nagoya Univ.) |
| |
14:50-15:05 |
Break ( 15 min. ) |
Wed, Mar 2 PM
15:05 - 16:45 |
| (5) |
15:05-15:30 |
An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization VLD2010-120 |
Yoshinori Shimada, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (6) |
15:30-15:55 |
Investigation and Evaluation of Sleep Signal Control based on a History Information for Fine-grain Power Gating VLD2010-121 |
Tetsuya Muto, Kimiyoshi Usami (Shibaura Inst. of Tech.) |
| (7) |
15:55-16:20 |
Low Power Design of Digital Circuits using Quasi-complementary MOS Gates VLD2010-122 |
Shuichi Sowa, Mineo Kaneko (JAIST) |
| (8) |
16:20-16:45 |
Reusable Constraints of Nano-watt BGR Circuits in CMOS Process Migration VLD2010-123 |
Gong Chen, Delong Yin, Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) |
| |
16:45-17:00 |
Break ( 15 min. ) |
Wed, Mar 2 PM
17:00 - 18:00 |
| (9) |
17:00-18:00 |
[Fellow Memorial Lecture]
Understanding CMOS Variability for More Moore VLD2010-124 |
Hidetoshi Onodera (Kyoto Univ./JST) |
Thu, Mar 3 AM
09:55 - 11:10 |
| (10) |
09:55-10:20 |
Semi-static TSPC DFF Using Split-output Latch VLD2010-125 |
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.) |
| (11) |
10:20-10:45 |
Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique VLD2010-126 |
Katsuhiko Iwai, Kenji Kojima, Mitsuru Shiozaki, Syunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.) |
| (12) |
10:45-11:10 |
Evaluation of Delay-Time Difference Distribution for the Delay-Time Difference Measurable Arbiter-PUF VLD2010-127 |
Takahiko Murayama, Mitsuru Shiozaki, Kota Furuhashi, Akitaka Fukushima, Takeshi Fujino (Ritsumeikan Univ.) |
| |
11:10-11:25 |
Break ( 15 min. ) |
Thu, Mar 3 AM
11:25 - 12:15 |
| (13) |
11:25-11:50 |
A Low Power Hardware Architecture for Parallel Group Signature Computation VLD2010-128 |
Sumio Morioka, Jun Furukawa, Kazue Sako (NEC) |
| (14) |
11:50-12:15 |
A scalable hardware architecture for real time image recognition VLD2010-129 |
Takashi Aoki, Eiichi Hosoya, Takuya Otsuka, Akira Onozawa (NTT) |
Thu, Mar 3 PM
13:45 - 15:25 |
| (15) |
13:45-14:10 |
A Circuit Synthesis for High Speed Memory Access in System LSI VLD2010-130 |
Kazuya Kishida, Takashi Kambe (Kinki Univ.) |
| (16) |
14:10-14:35 |
A Circuit Synthesis for Dynamic Reconfigurable Processor VLD2010-131 |
Nobuyuki Araki, Takashi Kambe (Kinki Univ.) |
| (17) |
14:35-15:00 |
A Circuit Design and Its Evaluation for Correlation Caluculation in Particle Tracking System VLD2010-132 |
Shouta Moriguchi, Takashi Kambe (Kinki Univ.) |
| (18) |
15:00-15:25 |
Delay Variation-Aware Datapath Synthesis for Improved Performance and Tunability VLD2010-133 |
Dang Yu, Mineo Kaneko (JAIST) |
| |
15:25-15:40 |
Break ( 15 min. ) |
Thu, Mar 3 PM
15:40 - 16:55 |
| (19) |
15:40-16:05 |
A Study for Evaluation of Statistical Maximum Operations for Gaussian Mixture Models VLD2010-134 |
Tamotsu Ishihara, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.) |
| (20) |
16:05-16:30 |
Performance Evaluation of Statistical Static Timing Analysis Using Gaussian Mixture Models VLD2010-135 |
Tomoyuki Fujimori, Shuji Tsukiyama (Chuo Univ), Masahiro Fukui (Ritsumeikan Univ) |
| (21) |
16:30-16:55 |
Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests VLD2010-136 |
Takanobu Shiki, Yasuhiro Takashima (Univ.of Kitakyushu), Yuichi Nakamura (NEC Corp.) |
Fri, Mar 4 AM
10:00 - 11:40 |
| (22) |
10:00-10:25 |
A Routing Method for Multi-Layer Single Flux Quantum Circuits with Wire Ordering based on Slack Allocation VLD2010-137 |
Shota Takeshima, Kazuyoshi Takagi, Masamitsu Tanaka (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) |
| (23) |
10:25-10:50 |
CRP : Efficient Topology Modification for Minimum Perturbation Placement Realization VLD2010-138 |
Yuki Kouno, Yasuhiro Takashima (Univ. of Kitakyushu), Atsushi Takahashi (Osaka Univ.) |
| (24) |
10:50-11:15 |
Fast Algorithm for All-Pair Shortest Path on DAG using CUDA VLD2010-139 |
Akihide Yamamura, Yasuhiro Takashima (Univ. of Kitakyushu) |
| (25) |
11:15-11:40 |
On Realization and Evaluation of Capacitors in Analog Integrated Circuits VLD2010-140 |
Atsushi Ochi, Ryoei Shimazu, Toru Fujimura, Shigetoshi Nakatake (Univ.of Kitakyushu) |
Fri, Mar 4 PM
13:10 - 14:50 |
| (26) |
13:10-13:35 |
An evaluation of error detection/correction circuits by gate level simulation VLD2010-141 |
Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) |
| (27) |
13:35-14:00 |
Behavior Verification of a Variable Latency Circuit on FPGA VLD2010-142 |
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Tech), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) |
| (28) |
14:00-14:25 |
Acceleration of Bounded Model Checking for Sequential Circuits with Two-phase Verification VLD2010-143 |
Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) |
| (29) |
14:25-14:50 |
Write Optimization for High-speed Non-volatile Memory Using Next State Function VLD2010-144 |
Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) |
| |
14:50-15:05 |
Break ( 15 min. ) |
Fri, Mar 4 PM
15:05 - 16:20 |
| (30) |
15:05-15:30 |
A scalable prototyping system for 3D-stacked LSI development VLD2010-145 |
Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) |
| (31) |
15:30-15:55 |
Performance Evaluation of Via Programmable ASIC Architecture VPEX3 VLD2010-146 |
Taisuke Ueoka, Tatsuya Kitamori, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) |
| (32) |
15:55-16:20 |
Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX VLD2010-147 |
Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Akihisa Yamada (Sharp)
E- :     a    s rp
Tel: +81-743-65-2531, Fax: +81-743-65-0554 |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
Last modified: 2011-02-21 16:33:33
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