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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2007)
Search Results: Keywords 'from:2008-01-16 to:2008-01-16'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 10:15 |
Kanagawa | Hiyoshi Campus, Keio University | [Invited Talk]
Flex Power FPGA Hanpei Koike (AIST) |
We have investigated Flex Power FPGA, in which fine-grain reconfigurable threshold voltage control enables substantial r... [more] | VLD2007-105 CPSY2007-48 RECONF2007-51 pp.1-6 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 12:55 |
Kanagawa | Hiyoshi Campus, Keio University | High speed control system using Multilevel control circuit Hiroaki Maekawa, Ryuichi Tanaka, Masatoshi Sekine (TUAT)  VLD2007-106 CPSY2007-49 RECONF2007-52 |
[more] | VLD2007-106 CPSY2007-49 RECONF2007-52 pp.7-12 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 13:20 |
Kanagawa | Hiyoshi Campus, Keio University | Scalable RHPC(Reconfigurable HPC) by using FPGA array Hiroaki Iijima, Kazuki Sato, Masatoshi Sekine (Tokyo Univ. of Agriculture and Technology) VLD2007-107 CPSY2007-50 RECONF2007-53 |
PGA array that interconnect many FPGA proposed as foundation for Large-scale operations. FPGA array we propose in this ... [more] |
VLD2007-107 CPSY2007-50 RECONF2007-53 pp.13-18 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 13:45 |
Kanagawa | Hiyoshi Campus, Keio University | Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs Yuzo Nishioka, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2007-108 CPSY2007-51 RECONF2007-54 |
In deep sub-micron process, the wire delay exceeds the switching delay. The wire delay is dominant in the total delay. F... [more] | VLD2007-108 CPSY2007-51 RECONF2007-54 pp.19-24 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 14:10 |
Kanagawa | Hiyoshi Campus, Keio University | An optimization method of DMA transfer for the SRC-6 reconfigurable machine Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2007-109 CPSY2007-52 RECONF2007-55 |
DMA transfer between a CPU and an FPGA often becomes a bottleneck of current reconfigurable machines. To mitigate this p... [more] | VLD2007-109 CPSY2007-52 RECONF2007-55 pp.25-30 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 14:45 |
Kanagawa | Hiyoshi Campus, Keio University | A study of the effectiveness of dynamic partial reconfiguration for size and power reduction Yohei Hori, Hirofumi Sakane, Kenji Toda (AIST) VLD2007-110 CPSY2007-53 RECONF2007-56 |
We evaluated the effectiveness of the partial reconfiguration in reducing area and power consumption of an FPGA-based ci... [more] | VLD2007-110 CPSY2007-53 RECONF2007-56 pp.31-36 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 15:10 |
Kanagawa | Hiyoshi Campus, Keio University | Development of verification and power estimation methodology for circuits with Run Time Power Gating Mitsutaka Nakata, Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Kimiyoshi Usami (S.I.T.), Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-111 CPSY2007-54 RECONF2007-57 |
When applying Run-Time Power Gating (RTPG) to a design，logic verification is one of the major problems．Gate-level simula... [more] | VLD2007-111 CPSY2007-54 RECONF2007-57 pp.37-42 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 15:35 |
Kanagawa | Hiyoshi Campus, Keio University | Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Mitsutaka Nakata, Kimiyoshi Usami (S.I.T.), Yohei Hasegawa, Naomi Seki, Hideharu Amano (Keio Univ.) VLD2007-112 CPSY2007-55 RECONF2007-58 |
Run Time Power Gating (RTPG) is a technology that reduces leakage power in a temporally/spatially fine-grained manner. T... [more] | VLD2007-112 CPSY2007-55 RECONF2007-58 pp.43-48 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 16:00 |
Kanagawa | Hiyoshi Campus, Keio University | An efficient algorithm for RTL power macro modeling and library building Masaaki Ohtsuki, Masato Kawai, Tatsuya Koyagi, Masahiro Fukui (Ritsumeikan Univ.) |
Due to the rapid growth of the electric systems, efficient and lowpower designs have been highly required. To satisfy th... [more] | VLD2007-113 CPSY2007-56 RECONF2007-59 pp.49-54 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 16:35 |
Kanagawa | Hiyoshi Campus, Keio University | Solving the Quadratic Assignment Problem by Hardware Based on a Systolic Algorithm Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) VLD2007-114 CPSY2007-57 RECONF2007-60 |
For the quadratic assignment problem (QAP), a heuristic algorithm based on tabu search, which is implemented as hardware... [more] | VLD2007-114 CPSY2007-57 RECONF2007-60 pp.55-60 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 17:00 |
Kanagawa | Hiyoshi Campus, Keio University | A Regular Expression String Matching Machine Allowing Pattern Setting During Execution Time and Its FPGA Implementation Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) VLD2007-115 CPSY2007-58 RECONF2007-61 |
In this paper, a high-speed string matching circuit for searching a pattern in a given text is proposed. In the circuit... [more] | VLD2007-115 CPSY2007-58 RECONF2007-61 pp.61-66 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 17:25 |
Kanagawa | Hiyoshi Campus, Keio University | Fast solution method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2 Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex) VLD2007-116 CPSY2007-59 RECONF2007-62 |
This paper proposes a fast calculation method of the set cover problem, which is implemented on reconfigurable processor... [more] | VLD2007-116 CPSY2007-59 RECONF2007-62 pp.67-72 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 17:50 |
Kanagawa | Hiyoshi Campus, Keio University | A Method of Design and Update for an Address Generator Using a Hybrid Method Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (K.I.T.) VLD2007-117 CPSY2007-60 RECONF2007-63 |
[more] | VLD2007-117 CPSY2007-60 RECONF2007-63 pp.73-78 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 08:40 |
Kanagawa | Hiyoshi Campus, Keio University | [Invited Talk]
ICCAD summary report Yusuke Matsunaga (Kyushu Univ.) VLD2007-118 CPSY2007-61 RECONF2007-64 |
This paper briefly summarizes the overview of ICCAD 2007, which was held in California, USA during Nov. 5 to Nov. 8. Al... [more] |
VLD2007-118 CPSY2007-61 RECONF2007-64 pp.1-6 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 09:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-119 CPSY2007-62 RECONF2007-65 |
As device feature size decreases, interconnection delay becomes the dominating factor of total delay. In addition, as ... [more] |
VLD2007-119 CPSY2007-62 RECONF2007-65 pp.7-12 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 09:40 |
Kanagawa | Hiyoshi Campus, Keio University | Scheduling and Memory Binding in High Level Synthesis for FPGAs Yuki Sagawa, Tsuyoshi Sadakata, Yusuke Matsunaga (Kyusyu Univ.) VLD2007-120 CPSY2007-63 RECONF2007-66 |
In High Level Synthesis for FPGAs,arrays in behavioral description may be bound to the same memory block since the numbe... [more] | VLD2007-120 CPSY2007-63 RECONF2007-66 pp.13-18 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 10:15 |
Kanagawa | Hiyoshi Campus, Keio University | Improvement in data communication between PEs for SIMD type processor MX core Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2007-121 CPSY2007-64 RECONF2007-67 |
We are researching about MX Core developed in Renesas Technology Corp.. MX Core is SIMD(Single Instruction Multiple Data... [more] | VLD2007-121 CPSY2007-64 RECONF2007-67 pp.19-24 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 10:40 |
Kanagawa | Hiyoshi Campus, Keio University | Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation Takahiro Kawahara, Shinobu Miwa, Hajime Shimada (Kyoto Univ.), Shin-ichiro Mori (Univ. of Fukui), Shinji Tomita (Kyoto Univ.) VLD2007-122 CPSY2007-65 RECONF2007-68 |
We are developing the parallel volume rendering accelerator VisA.VisA communicates with one-way link over DVI-D which is... [more] | VLD2007-122 CPSY2007-65 RECONF2007-68 pp.25-30 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 11:05 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication Shotaro Saito, Yasufumi Sugimori, Yoshinori Kohama, Tadahiro Kuroda, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-123 CPSY2007-66 RECONF2007-69 |
This paper describes the physical design and evaluation of 3-D dynamically reconfigurable processor MuCCRA-Cube which co... [more] | VLD2007-123 CPSY2007-66 RECONF2007-69 pp.31-36 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 11:30 |
Kanagawa | Hiyoshi Campus, Keio University | An effective data I/O mechanism utilizing FIFOs for an array processor Yuusuke Nomoto, Yuka Sato, Toshiaki Miyazaki (Univ. of Aizu) VLD2007-124 CPSY2007-67 RECONF2007-70 |
Data I/O management is very important to handle huge data effectively in signal and image processing with array processo... [more] | VLD2007-124 CPSY2007-67 RECONF2007-70 pp.37-42 |
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