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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 09:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | All Binarized Conventional Neural Network and its Implementation on an FPGA
-- FPT2017 Design Competition Report -- Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech)  VLD2017-63 CPSY2017-107 RECONF2017-51 |
[more] | VLD2017-63 CPSY2017-107 RECONF2017-51 pp.7-11 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 10:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Titech) VLD2017-64 CPSY2017-108 RECONF2017-52 |
[more] | VLD2017-64 CPSY2017-108 RECONF2017-52 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 15:30 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Study on Target Pin-Pairs Selection for Set-Pair Routing Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech.) VLD2017-59 DC2017-65 |
[more] | VLD2017-59 DC2017-65 pp.235-240 |
| RECONF | 2017-09-25 14:20 |
Tokyo | DWANGO Co., Ltd. | A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization Tomoya Fujii, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) RECONF2017-26 |
For a pre-trained deep convolutional neural network (CNN) for an embedded system, a high-speed and a low power consumpt... [more] |
RECONF2017-26 pp.25-30 |
| RECONF | 2017-09-26 10:00 |
Tokyo | DWANGO Co., Ltd. | GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato (Tokyo Inst. of Tech.) RECONF2017-31 |
[more] | RECONF2017-31 pp.51-56 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-07-27 15:45 |
Akita | Akita Atorion-Building (Akita) | Consideration of All Binarized Convolutional Neural Network Masayuki Shimoda, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) CPSY2017-28 |
A pre-trained convolutional neural network (CNN) is a feed-forward computation perspective, which is widely used for the... [more] | CPSY2017-28 pp.131-136 |
| SIP, CAS, MSS, VLD | 2017-06-20 15:30 |
Niigata | Niigata University, Ikarashi Campus | Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit Yuta Ukon, Shimpei Sato, Atsushi Takahashi (Tokyo Inst. of Tech.) CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23 |
There are a lot of high load processing that is not required high accuracy at the data center. An approximate computing ... [more] | CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23 pp.119-124 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 14:20 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | RECONF2017-2 |
[more] | RECONF2017-2 pp.7-11 |
| VLD | 2017-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering Shohei Handa, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-111 |
[more] | VLD2016-111 pp.55-60 |
| VLD | 2017-03-02 11:20 |
Okinawa | Okinawa Seinen Kaikan | Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-113 |
In current semiconductor design, high quality and short time design is required. In an advanced lithography technology... [more] |
VLD2016-113 pp.67-72 |
| VLD | 2017-03-02 11:45 |
Okinawa | Okinawa Seinen Kaikan | Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing Shun Sugihara, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2016-114 |
In printed circuit board, to meet requirements such as delay and noise, routing of each net is necessary to achieve its... [more] |
VLD2016-114 pp.73-78 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 09:25 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH) VLD2016-95 CPSY2016-131 RECONF2016-76 |
When variable latency for digital circuits are assumed, circuits can work with a small clock period that has the possib... [more] |
VLD2016-95 CPSY2016-131 RECONF2016-76 pp.165-170 |
| CPSY, IPSJ-ARC | 2015-10-08 10:00 |
Chiba | Makuhari-messe | [Technology Exhibit]
Demonstration of an application analysis tool "Exana" for assisting CPU performance tuning Yukinori Sato, Shimpei Sato, Toshio Endo (Tokyo Tech) CPSY2015-48 |
We have been developing Exana tool set that can transparently analyze application code execution at run time using pre-c... [more] | CPSY2015-48 pp.11-13 |
| RECONF | 2014-09-18 15:45 |
Hiroshima | Challenge for Ultrafast 10K-Node NoC emulation on FPGA Thiem Van Chu, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) RECONF2014-21 |
With thousands of cores in the near future NoC architectures, the simulation time is a serious problem that makes archit... [more] | RECONF2014-21 pp.23-28 |
|
| CPSY | 2013-10-03 10:45 |
Chiba | Makuhari Messe | Design of a translator to Verilog HDL from hardware modeling language ArchHDL Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-31 |
We have proposed ArchHDL as a new language for hardware RTL modeling. In ArchHDL, we realized continuous assignment and ... [more] | CPSY2013-31 pp.1-6 |
| CPSY | 2013-10-03 11:10 |
Chiba | Makuhari Messe | TMR execution on SmartCore system for dependable many-core processors Ryosuke Sasakawa, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-32 |
In order to improve the chip-level dependability, we have proposed SmartCore system, NoC-based DMR(Dual Modular Redundan... [more] | CPSY2013-32 pp.7-12 |
| CPSY | 2009-11-20 15:55 |
Kyoto | Campus Plaza Kyoto | A Study of Task Allocation Problem for Many-core Processor with Consideration of Network Traffic Shintaro Sano, Masahiro Sano, Shimpei Sato (Tokyo Inst. of Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech./JST), Kenji Kise (Tokyo Inst. of Tech.) CPSY2009-40 |
In many-core architecture that has dozens of cores in processor, it is important to improve performance by using paralle... [more] | CPSY2009-40 pp.31-36 |
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