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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 13:20 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | An aging aware high-level synthesis algorithm with floorplanning Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2016-68 DC2016-62 |
(To be available after the conference date) [more] | VLD2016-68 DC2016-62 pp.141-146 |
| VLD, IPSJ-SLDM | 2016-05-11 14:30 |
Fukuoka | Kitakyushu International Conference Center | A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4 |
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] | VLD2016-4 pp.41-46 |
| VLD | 2016-03-01 15:10 |
Okinawa | Okinawa Seinen Kaikan | FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] | VLD2015-127 pp.93-98 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-06 16:05 |
Kagoshima | A proposal of placement optimization algorithm by introducing TSV module Atsushi Murata, Tomohiro Inaba, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) CPSY2014-169 DC2014-95 |
The performance and the power efficiency of VLSI are expected to be significantly improved by the development of 3D stac... [more] | CPSY2014-169 DC2014-95 pp.43-48 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-85 DC2014-39 |
Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image pro- cessing and computer... [more] | VLD2014-85 DC2014-39 pp.99-104 |
| NLP, CAS | 2012-09-21 11:45 |
Kochi | Eikokuji Campus, University of Kochi | Representation of a Box Partitioned by Rectangles Toshihiko Takahashi (: Niigata Univ.) CAS2012-43 NLP2012-69 |
For VLSI layout design, many floorplan representations have been proposed since the mid-1990s. Especially representatio... [more] | CAS2012-43 NLP2012-69 pp.71-74 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 15:25 |
Kanagawa | Hiyoshi Campus, Keio University | Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) |
(To be available after the conference date) [more] | |
| SIP, CAS, CS | 2010-03-02 13:45 |
Okinawa | Hotel Breeze Bay Marina, Miyakojima | [Poster Presentation]
2.5-dimensional FT-Squeeze
-- Permutation Representation of Stacked Rectangular Drawings -- Toshihiko Takahashi (Niigata Univ.) CAS2009-121 SIP2009-166 CS2009-116 |
In this report, we introduce a permutation representation of stacked rectangular drawings. This representation does not ... [more] | CAS2009-121 SIP2009-166 CS2009-116 pp.239-240 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 14:45 |
Kochi | Kochi City Culture-Plaza | A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI Hidekazu Seto, Kazuhito Ito (Saitama Univ.) VLD2009-45 DC2009-32 |
The energy dissipation by data communications on a LSI chip depends on the layout of modules as well as how data are com... [more] | VLD2009-45 DC2009-32 pp.25-30 |
| VLD | 2009-03-12 14:15 |
Okinawa | Automatic generation of Network-on-Chip topology under link length and latency constraint Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST) VLD2008-148 |
With wire delay becoming dominant compared to transistor delay in deep-submicron era, the performance of SoC is more aff... [more] | VLD2008-148 pp.129-134 |
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| VLD, CAS, SIP | 2008-06-27 11:15 |
Hokkaido | Hokkaido Univ. | An asymptotic estimate of the numbers of rectangular drawings or floorplans Ryo Fujimaki (Niigata Univ.), Youhei Inoue (Renesas Technology), Toshihiko Takahashi (Niigata Univ.) CAS2008-25 VLD2008-38 SIP2008-59 |
A subdivision of a rectangle into rectangular faces with horizontal and vertical line segments is called rectangular d... [more] |
CAS2008-25 VLD2008-38 SIP2008-59 pp.37-41 |
| CS, SIP, CAS | 2008-03-07 09:50 |
Yamaguchi | Yamaguchi University | Improved Method of Multi-Branched Bus Driven Floorplanning Yosuke Taira, Kunihiro Fujiyoshi (TUAT) CAS2007-132 SIP2007-207 CS2007-97 |
sequence-pair, バスドリブン, フロアプラン設計, 増加部分列, 減少部分列 sequence-pair, Bus-driven, floorplanning, increasing subsequence, decre... [more] |
CAS2007-132 SIP2007-207 CS2007-97 pp.41-46 |
| VLD, ICD | 2008-03-05 15:20 |
Okinawa | TiRuRu | Analog Floorplan with Soft-Module Configuration Kentarou Murata, Kazuya Sasaki, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2007-142 ICD2007-165 |
In MOS analog design, the transistor size is increasing as the supply voltage becomes lower, and the layout configurat... [more] |
VLD2007-142 ICD2007-165 pp.31-36 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 15:45 |
Fukuoka | Kitakyushu International Conference Center | A Resource Binding Method for Reducing Power Consumption of LSI Data Communications Hidekazu Seto, Kazuhito Ito (Saitama Univ.) VLD2007-86 DC2007-41 |
The power consumption by data communications on a LSI chip depends on the layout of modules as well as how data are comm... [more] | VLD2007-86 DC2007-41 pp.25-30 |
| VLD, IPSJ-SLDM | 2007-05-11 14:10 |
Kyoto | Kyodai Kaikan | An algorithm of power grid optimization for high-level floorplan Takayuki Hayashi, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ.) |
Recent rapid growth of the narrow and fine patterning technology faces many difficulties of power grid design , e.g. IR ... [more] | VLD2007-15 pp.49-54 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2007-01-17 16:00 |
Tokyo | Keio Univ. Hiyoshi Campus | A Parallel Algorithm Based on Genetic Algorithm and Tabu Search for LSI Floorplanning and Its Implementation on a PC Cluster Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) |
This paper proposes a parallel floorplanning algorithm for VLSI floorplanning, which was based on genetic algorithm (GA)... [more] | VLD2006-90 CPSY2006-61 RECONF2006-61 pp.31-36 |
| NLP | 2006-03-20 15:20 |
Tokyo | Hosei Univ.(Ichigaya Campus) | Two-Staged Tabu Search for Floorplan Problem Using O-Tree Structure Kimihiko Numayama (Shizuoka Univ), Hiroshi Ninomiya (SIT), Hideki Asai (Shizuoka Univ) |
This papar describes the two-staged Tabu search for the non-slicing floorplan problem using the orderd tree representat... [more] | NLP2005-146 pp.53-58 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-25 16:50 |
Kanagawa | Architecture for Crossover based on Sequence Pair Ryousuke Kanemitsu, Akinori Bito, Masaya Yoshikawa, Hidekazu Terai (Ritsumeikan University) |
The floor planning technique that uses GA based on the sequence pair for the solution search is proposed and it obtains ... [more] | VLD2004-109 CPSY2004-75 pp.69-74 |
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