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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| KBSE, SC | 2023-11-17 16:20 |
Miyagi | Sento Kaikan | A technique of autonomous control of IP network camera with PTZ functions Kazutaka Kikuta, Ken. T. Murata, Yuki Murakami (NICT), Takamichi Mizuhara, Toshiki Aoki (CLT)  KBSE2023-38 SC2023-21 |
Resilient Natural Environment Measurement Project in National Institute of Information and Communications Technology (NI... [more] | KBSE2023-38 SC2023-21 pp.37-39 |
| ASN, SRW (Joint) |
2018-11-05 14:20 |
Tokyo | Tokyo Denki University, Tokyo Senju Campus | A Study on a Feature Based Clustering and Decision Tree Regressions for Estimating the Bubble Point Pressure of Crude Oils Meshal Almashan, Yoshiaki Narusue, Hiroyuki Morikawa (The Univ. of Tokyo) ASN2018-68 |
Bubble point pressure (Pb) is one of the most important Pressure-Volume-Temperature (PVT) properties of any crude oil sy... [more] | ASN2018-68 pp.75-80 |
| ICD, CPSY, CAS | 2017-12-14 10:40 |
Okinawa | Art Hotel Ishigakijima | Performance Analysis of Level-Cross Detection Method based on Stochastic Comparator Taiki Sugiyama, Tetsuya Iizuka (Univ. of Tokyo), Takahiro Yamaguchi (Advantest), Toru Nakura, Kunihiro Asada (Univ. of Tokyo) CAS2017-66 ICD2017-54 CPSY2017-63 |
ADC based on level-cross detection quantizes time rather than voltage. When the clock frequency is doubled, SNR of ADC i... [more] | CAS2017-66 ICD2017-54 CPSY2017-63 pp.15-20 |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | Maximum power estimator for ultra-low power energy harvesters Hiroki Asano, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) CAS2017-98 ICD2017-86 CPSY2017-95 |
In this paper, we propose a fully integrated and area-efficient resistor-less relaxation oscillator (ROSC) for ultra-low... [more] | CAS2017-98 ICD2017-86 CPSY2017-95 p.141 |
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 15:00 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) | A fully on-chip, ultra-low power RC oscillator with current mode architecture for real time clock applications Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) EMD2016-85 MR2016-57 SCE2016-63 EID2016-64 ED2016-128 CPM2016-129 SDM2016-128 ICD2016-116 OME2016-97 |
A compact and low-power current-mode RC oscillator (RCO) with process, voltage, and temperature (PVT) stability has been... [more] | EMD2016-85 MR2016-57 SCE2016-63 EID2016-64 ED2016-128 CPM2016-129 SDM2016-128 ICD2016-116 OME2016-97 pp.81-86 |
| ICD, SDM, ITE-IST [detail] | 2016-08-01 10:00 |
Osaka | Central Electric Club | A fast-start up and fully-integrated 32-MHz clock generator for intermittent VLSI systems Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) SDM2016-49 ICD2016-17 |
This paper proposes a fully integrated 32-MHz relaxation oscillator (ROSC) capable of fast start-up time operation f... [more] |
SDM2016-49 ICD2016-17 pp.3-8 |
| ICD, CPSY | 2015-12-18 16:45 |
Kyoto | Kyoto Institute of Technology | Autonomously Tracking PVT Variations of Pulse Width Controlled PLL using Hill-Climbing Method Toi Takashi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (Tokyo Univ.) ICD2015-95 CPSY2015-108 |
[more] | ICD2015-95 CPSY2015-108 pp.135-140 |
| MW (2nd) |
2014-11-26 - 2014-11-28 |
Overseas | King Mongkut's Institute of Technology Ladkrabang (KMITL), Bangkok | A PVT-Robust VCO with Tail-Current Modulation Scheme Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokodai) |
This paper proposes a VCO topology in which the tail-current is adaptively modulated for enhancing the current efficienc... [more] | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:15 |
Oita | B-ConPlaza | Design of Flip-Flop with Timing Error Tolerance Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33 |
Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] | VLD2014-79 DC2014-33 pp.45-50 |
| ICD, SDM | 2014-08-05 15:20 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | CMOS Relaxation Oscillator for a Real-Time Clock Application Keishi Tsubaki, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) SDM2014-80 ICD2014-49 |
This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application... [more] | SDM2014-80 ICD2014-49 pp.99-104 |
| DC | 2011-02-14 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Variation Aware Test Methodology Based on Statistical Static Timing Analysis Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) DC2010-62 |
The continuing miniaturization of LSI dimension may cause parametric faults which exceed the specification due to proces... [more] | DC2010-62 pp.21-26 |
| ED, MW | 2010-01-15 10:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Pseudo Sinusoidal Generator with PVT Compensation Circuit using InP HBTs
-- For Linear Control of Vector-Sum Phase Shifter -- Hideyuki Nosaka, Munehiko Nagatani, Shogo Yamanaka, Kimikazu Sano, Koichi Murata (NTT Corp.) ED2009-192 MW2009-175 |
A pseudo-sinusoidal generator is needed to realize a voltage-controlled vector-sum phase shifter that has linear phase c... [more] | ED2009-192 MW2009-175 pp.99-103 |
| ICD, SDM | 2007-08-23 15:25 |
Hokkaido | Kitami Institute of Technology | A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors Kazuki Fukuoka, Osamu Ozawa, Ryo Mori, Yasuto Igarashi, Toshio Sasaki, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi (Renesas Technology) SDM2007-153 ICD2007-81 |
A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing t... [more] | SDM2007-153 ICD2007-81 pp.69-73 |
| ICD, ITE-IST | 2007-07-27 09:45 |
Hyogo | A PVT Tolerant PLL with On-Chip Loop-Transfer-Function Calibration Circuit M.Kondou (Fujitsu Laboratoried Ltd), T.Mori (Fujitsu Limited) ICD2007-57 |
A PVT tolerant PLL architecture which uses two on-chip digital calibration circuits to maintain loop transfer function i... [more] | ICD2007-57 pp.117-121 |
|
| ICD, VLD | 2006-03-10 15:35 |
Okinawa | An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design Takayuki Gyohten, Fukashi Morishita (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltag... [more] | VLD2005-132 ICD2005-249 pp.61-66 |
|
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 09:00 |
Miyagi | Ichinobo, Sakunami-Spa | A Phase Noise Minimization of CMOS LC-VCOs Over Wide Tuning Range and Large PVT Variations Daisuke Miyashita, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada (Toshiba Corp.) |
An automatic amplitude control circuit to minimize the phase noise of a LC-VCO is proposed and implemented by a 0.18-μm ... [more] | SIP2005-115 ICD2005-134 IE2005-79 pp.1-5 |
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