Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, IPSJ-ARC |
2016-10-06 10:00 |
Chiba |
Makuhari-messe |
[Technology Exhibit]
Security technologies for non-volatile memory in IoT devices
-- Mechanisms for on-chip MCU and off-chip memory system -- Mikio Hashimoto, Yoshiyuki Amanuma, Kentaro Umesawa, Ryuichi Koike, Jun Kanai, Naoko Yamada (Toshiba) CPSY2016-51 |
Non-volatile memory content modification is serious issues on IoT appliances, since evil effects continue over power cyc... [more] |
CPSY2016-51 pp.37-42 |
RECONF |
2016-05-19 17:30 |
Kanagawa |
FUJITSU LAB. |
[Invited Talk]
Overviews on key technologies to substantialize 'IoT society' Toshihiro Matsui, Hisashi Sekine, Hideki Hayashi, Hiroaki Ohkubo, Hirotaka Sunaguchi, Naoyuki Matsuo, Yoshitatsu Sato (NEDO TSC) RECONF2016-16 |
Regarding non-volatile memories, sensors, embedded software, and cyber security as the key components in the coming IoT ... [more] |
RECONF2016-16 pp.77-82 |
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] |
2016-01-21 11:20 |
Kanagawa |
Hiyoshi Campus, Keio University |
An Architectural Optimization for Software Defined SSD using Full System Simulator Shun Gokita, Satoshi Kazama, Seiki Shibata, Shinya Kuwamura, Eiji Yoshida, Junji Ogawa (FLL) VLD2015-103 CPSY2015-135 RECONF2015-85 |
In recent years, a kind of software-defined SSD which has a Flash control layer (FTL) in software teared out of hardware... [more] |
VLD2015-103 CPSY2015-135 RECONF2015-85 pp.197-202 |
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] |
2016-01-21 14:15 |
Kanagawa |
Hiyoshi Campus, Keio University |
Write-Reduction using Encoding data on MLC for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-107 CPSY2015-139 RECONF2015-89 |
There is a movement to use the non-volatile memory to the important main memory in von Neumann computer.
Non-volatile m... [more] |
VLD2015-107 CPSY2015-139 RECONF2015-89 pp.221-225 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 15:00 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-76 DC2015-72 |
Recently, due to low leakage power and non-volatility, the non-volatile memory technology has advanced remarkably.
Howe... [more] |
VLD2015-76 DC2015-72 pp.249-253 |
CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-06 14:30 |
Oita |
B-Con Plaza (Beppu) |
Performance tuning methods for out-of-core stencil computations with flash SSDs Hiroko Midorikawa, Hideyuki Tan (Seikei Univ.) CPSY2015-41 |
This report proposes several performance tuning methods to use flash SSDs as an extension to main memory. It also invest... [more] |
CPSY2015-41 pp.241-246 |
ICD |
2015-04-16 16:40 |
Nagano |
|
[Panel Discussion]
Advanced semiconductor memories in cloud computing and high-performance computing Koji Nii (Renesas Electronics), Kousuke Miyaji (Shinshu Univ.), Ryousei Takano (AIST), Kensei Takagi, Toru Miwa (SanDisk) ICD2015-7 |
(To be available after the conference date) [more] |
ICD2015-7 p.31 |
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] |
2015-03-07 09:20 |
Kagoshima |
|
A Study on a Power Efficient Neurochip with Non-Volatile Memory Jun Tomii, Masaaki Kondo, Hiroshi Nakamura (Univ. Tokyo) CPSY2014-176 DC2014-102 |
Along with the evolution of machine learning techniques, neurochips, which are designed for fast neural network processi... [more] |
CPSY2014-176 DC2014-102 pp.83-88 |
VLD |
2015-03-03 16:15 |
Okinawa |
Okinawa Seinen Kaikan |
[Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-173 |
Non-volatile memory is superior to SRAM in terms of its high density and low leakage power
but it consumes larger writ... [more] |
VLD2014-173 p.115 |
ICD, CPSY |
2014-12-01 15:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Poster Presentation]
A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ) ICD2014-82 CPSY2014-94 |
Demands for low energy microcontrollers which are used in sensor nodes have been increasing in recent years. Also most m... [more] |
ICD2014-82 CPSY2014-94 p.43 |
ICD, CPSY |
2014-12-01 15:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Poster Presentation]
Evaluation of ReRAM write characteristics Shin Nishikawa (Chuo Univ), Sheyang Ning (Univ. of Tokyo), Ken Takeuchi (Chuo Univ) ICD2014-89 CPSY2014-101 |
Resistance random access memory (ReRAM) is a type of the next generation non-volatile memory due to its faster write spe... [more] |
ICD2014-89 CPSY2014-101 p.57 |
ICD, CPSY |
2014-12-01 15:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Poster Presentation]
Reliability evaluation of Carbon Nanotube (CNT) based non-volatile memory Eisuke Yanagizawa (Chuo Univ.), Sheyang Ning (Chuo Univ./Tokyo Univ.), Ken Takeuchi (Chuo Univ.) ICD2014-91 CPSY2014-103 |
Carbon nanotube (CNT) based non-volatile memory (NRAM) write and erase are implemented using Reset/Set program pulses. I... [more] |
ICD2014-91 CPSY2014-103 p.61 |
IA |
2014-11-27 13:00 |
Tottori |
Green-Squalle Sekigane (Tottori) |
The High Reliability Network Equipment utilizing non-Volatile Data Tomoyuki Oku (Hitachi), Yoshifumi Atarashi (ALAXALA Networks) IA2014-67 |
Event log information stored in communication equipment (CE) is useful for fault analysis. However, a number of event lo... [more] |
IA2014-67 pp.31-36 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita |
B-ConPlaza |
Energy evaluation of bit-write reduction method based on state encoding limiting maximum and minimum Hamming distances for non-volatile memories Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-105 DC2014-59 |
Data stored in non-volatile memories may be destructed due to crosstalk and radiation but we can restore their data by u... [more] |
VLD2014-105 DC2014-59 pp.221-226 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita |
B-ConPlaza |
Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-106 DC2014-60 |
Non-volatile memory has many advantages such as low leakage power and
non-volatility. However, there are problems that ... [more] |
VLD2014-106 DC2014-60 pp.227-232 |
CPSY |
2014-10-10 13:50 |
Chiba |
Meeting Room 303, International Conference Hall, Makuhari-Messe |
An Evaluation of Stencil Computation using Flash Storage with Asynchronous Block Device I/O Hideyuki Tan, Hiroko Midorikawa (Seikei Univ./JST) CPSY2014-52 |
In order to execute stencil calculations of the large scale problems beyond physical memory, we evaluated three differen... [more] |
CPSY2014-52 pp.31-36 |
CAS, SIP, MSS, VLD, SIS [detail] |
2014-07-11 13:40 |
Hokkaido |
Hokkaido University |
Write Reduction of Internal Registers for Non-volatile RISC Processors Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 |
Recently next-generation non-volatile memories based on MTJ (Magnetic Tunnel Junction) have been paid attention because ... [more] |
CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 pp.213-218 |
IPSJ-SLDM, CPSY, RECONF, VLD [detail] |
2014-01-29 15:15 |
Kanagawa |
Hiyoshi Campus, Keio University |
A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84 |
In order to reduce the power consumption of LSI,
unnecessary parts should be powered off with fine granularity,
and c... [more] |
VLD2013-130 CPSY2013-101 RECONF2013-84 pp.167-172 |
ICD |
2014-01-28 15:00 |
Kyoto |
Kyoto Univ. Tokeidai Kinenkan |
[Poster Presentation]
Program and erase characteristic variation of Carbon Nanotube(CNT) based non-volatile memory Kazuya Shimomura (Chuo Univ.), Sheyang Ning (Chuo Univ./Univ. of Tokyo), Ken Takeuchi (Chuo Univ.) ICD2013-121 |
The carbon nanotube (CNT) based non-volatile memory is similar as the resistive RAM (ReRAM) that the cell resistance can... [more] |
ICD2013-121 p.51 |
ICD |
2014-01-28 15:00 |
Kyoto |
Kyoto Univ. Tokeidai Kinenkan |
[Poster Presentation]
Control of ReRAM resistance Tatsuya Fujii, Tomoko Ogura Iwasaki, Ken Takeuchi (Chuo Univ) ICD2013-128 |
ReRAM is being developed and considered as a next-generation non-volatile memory. It shows excellent performances such a... [more] |
ICD2013-128 p.65 |