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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2022)
Search Results: Keywords 'from:2023-03-01 to:2023-03-01'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-02 14:15 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits [Memorial lecture] Dehua Liang (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.), Noriyuki Miura, Jun Shiomi (Osaka Univ.)  VLD2022-93 HWS2022-64 |
Voltage scaling is a promising approach for energy efficiency but also brings challenges to guaranteeing stable circuit ... [more] | VLD2022-93 HWS2022-64 p.111 |
| HWS, VLD | 2023-03-02 14:40 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
A method for synthesizing quantum circuits satisfying NNA constraints using SMT solvers Kyehei Seino, Shigeru Yamashita (Ritsumeikan University) VLD2022-94 HWS2022-65 |
It is natural to assume that we can perform quantum operations be- tween only two adjacent physical qubits (quantum bit... [more] |
VLD2022-94 HWS2022-65 p.112 |
| HWS, VLD | 2023-03-02 15:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
Secure Cache System against On-Chip Threats Keisuke Kamahori, Shinya Takamaeda (UTokyo) VLD2022-95 HWS2022-66 |
In this paper, we propose a new threat model for secure processor design that considers on-chip threats. Also, we desi... [more] |
VLD2022-95 HWS2022-66 pp.113-118 |
| HWS, VLD | 2023-03-02 15:45 |
Okinawa | (Primary: On-site, Secondary: Online) |
Hiding Memory Structure for IP Protection Sun Tanaka, Shinya Takamaeda (UTokyo) VLD2022-96 HWS2022-67 |
This paper proposes a concept and a method of hiding memory structure for IP protection. [more] | VLD2022-96 HWS2022-67 pp.119-124 |
| HWS, VLD | 2023-03-02 16:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
Multiple Constant Convolution with Minimum Number of Full Adders. Kota Kuga, Shinya Takamaeda (UTokyo) VLD2022-97 HWS2022-68 |
[more] | VLD2022-97 HWS2022-68 pp.125-130 |
| HWS, VLD | 2023-03-02 16:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Reducing Conflict Misses with Multiple Indexings in Compressed Caches Tasuku Fukami, Shinya Takamaeda (UTokyo) VLD2022-98 HWS2022-69 |
Cache memory is a common hardware mechanism that improves memory access performance. To enlarge cache capacity virtually... [more] | VLD2022-98 HWS2022-69 pp.131-136 |
| HWS, VLD | 2023-03-02 17:15 |
Okinawa | (Primary: On-site, Secondary: Online) |
Communication-Efficient Federated Learning with Gradient Boosting Decision Trees Kotaro Shimamura, Shinya Takamaeda (UTokyo) VLD2022-99 HWS2022-70 |
Federated learning (FL) is a machine learning method in which clients learn cooperatively without disclosing private dat... [more] | VLD2022-99 HWS2022-70 pp.137-142 |
| HWS, VLD | 2023-03-03 09:30 |
Okinawa | (Primary: On-site, Secondary: Online) |
Global routing method imitating car path search Yusuke Yamaguchi, Kunihiro Fujiyoshi (TUAT) VLD2022-100 HWS2022-71 |
Routing in LSI layout design is divided into two stages: global routing and detailed routing. In global routing, a path ... [more] | VLD2022-100 HWS2022-71 pp.143-148 |
| HWS, VLD | 2023-03-03 09:55 |
Okinawa | (Primary: On-site, Secondary: Online) |
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat) VLD2022-101 HWS2022-72 |
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] | VLD2022-101 HWS2022-72 pp.149-154 |
| HWS, VLD | 2023-03-03 10:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (JEDAT) VLD2022-102 HWS2022-73 |
In analog integrated circuits, designs usually rely on the relative accuracy of device characteristics. The purpose of t... [more] | VLD2022-102 HWS2022-73 pp.155-160 |
| HWS, VLD | 2023-03-03 11:00 |
Okinawa | (Primary: On-site, Secondary: Online) |
Yusei Yano, Shinji Nozaki, Tomohide Aizawa, Yukihide Kohira (Univ. of Aizu) VLD2022-103 HWS2022-74 |
(To be available after the conference date) [more] | VLD2022-103 HWS2022-74 pp.161-166 |
| HWS, VLD | 2023-03-03 11:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.) VLD2022-104 HWS2022-75 |
(To be available after the conference date) [more] | VLD2022-104 HWS2022-75 pp.167-172 |
| HWS, VLD | 2023-03-03 11:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Seed Selection Method to Minimize Test Application Time for Logic BIST Using Pseudo Boolean Optimization Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2022-105 HWS2022-76 |
[more] | VLD2022-105 HWS2022-76 pp.173-178 |
| HWS, VLD | 2023-03-03 13:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
High-Performance and Programmer-Friendly Secure Non-Volatile Memory using Temporal Memory-Access Redirection Ryo Koike, Shinya Takamaeda (UTokyo) VLD2022-106 HWS2022-77 |
Byte-addressable non-volatile memory (NVM) has two challenges, performance degradation due to high-latency integrity tre... [more] | VLD2022-106 HWS2022-77 pp.179-184 |
| HWS, VLD | 2023-03-03 13:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on Function Modification Circuit Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) VLD2022-107 HWS2022-78 |
In recent years, with the increase of VLSI integration, semiconductor design companies to design a VLSI have tended to u... [more] | VLD2022-107 HWS2022-78 pp.185-190 |
| HWS, VLD | 2023-03-03 14:15 |
Okinawa | (Primary: On-site, Secondary: Online) |
N/A Yuka Ikegami, Kazuki Yamashita (Waseda Univ.), Kento Hasegawa, Kazuhide Fukushima, Shinsaku Kiyomoto (KDDI Research, Inc.), Nozomu Togawa (Waseda Univ.) VLD2022-108 HWS2022-79 |
N/A [more] | VLD2022-108 HWS2022-79 pp.191-196 |
| HWS, VLD | 2023-03-03 14:40 |
Okinawa | (Primary: On-site, Secondary: Online) |
Toggle-based simulation of side-channel attack against multiplier for pairing-based cryptography Saito Kikuoka, Makoto Ikeda (Tokyo Univ.) VLD2022-109 HWS2022-80 |
Pairing-based cryptography is more secure than RSA with a shorter key length, but it is computationally expensive and mo... [more] | VLD2022-109 HWS2022-80 pp.197-202 |
| HWS, VLD | 2023-03-03 15:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
Design optimization of TFHE-based 4+ input homomorphic logic gates by error controlling Yinfan Zhao, Makoto Ikeda (Tokyo Univ.) VLD2022-110 HWS2022-81 |
Fully homomorphic encryption (FHE) is a way to delegate the processing of the data without giving a way access to it. FH... [more] | VLD2022-110 HWS2022-81 pp.203-208 |
| HWS, VLD | 2023-03-03 15:45 |
Okinawa | (Primary: On-site, Secondary: Online) |
Study of Intrinsic ID extracted from RG-DTM Arbiter PUF implemented on FPGA Mika Sakai, Tatsuya Oyama, Kota Yoshida (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) VLD2022-111 HWS2022-82 |
We studied the implementation method of PUF for generating a unique ID on FPGA. We adopted a method of controlling the p... [more] | VLD2022-111 HWS2022-82 pp.209-214 |
| HWS, VLD | 2023-03-03 16:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
NA Ryusei Eda, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.) VLD2022-112 HWS2022-83 |
(To be available after the conference date) [more] | VLD2022-112 HWS2022-83 pp.215-220 |
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