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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2017-04-21 10:25 |
Tokyo | [Invited Lecture]
A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time Yohei Sawada, Makoto Yabuuchi, Masao Morimoto (REL), Toshiaki Sano (RSD), Yuichiro Ishii, Shinji Tanaka (REL), Miki Tanaka (RSD), Koji Nii (REL)  ICD2017-12 |
[more] | ICD2017-12 pp.63-65 |
|
| DC | 2017-02-21 12:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design) DC2016-77 |
Today, advancements of semiconductor technology have progress to high integration of LSI circuits. A technique which ke... [more] |
DC2016-77 pp.17-22 |
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 15:25 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) | A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto (Renesas Electronics), Yuta Yoshida, Ken Shibata, Toshiaki Sano (Renesas System Design), Shinji Tanaka, Koji Nii (Renesas Electronics) EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98 |
We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which ena... [more] | EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98 pp.87-92 |
| ICD, SDM, ITE-IST [detail] | 2016-08-03 13:20 |
Osaka | Central Electric Club | [Invited Talk]
A 16nm FinFET Heterogeneous Nona-Core SoC Supporting Functional Safety Standard ISO26262 ASIL B Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji (Renesas System Design), Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita (Renesas Electronics) SDM2016-64 ICD2016-32 |
This paper presents an SoC for the next generation of car infotainment, achieving high performance powered by nine heter... [more] | SDM2016-64 ICD2016-32 pp.105-110 |
| ICD | 2016-04-14 10:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A Cost Effective Test Screening Method on 40-nm 4-Mb Embedded SRAM for Low-power MCU Yuta Yoshida (RSD), Yoshisato Yokoyama, Yuichiro Ishii (Renesas Electronics), Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi (RSD), Koji Nii (Renesas Electronics) ICD2016-1 |
An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micr... [more] | ICD2016-1 pp.1-6 |
| SDM | 2016-01-28 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas) SDM2015-125 |
[more] | SDM2015-125 pp.21-25 |
| SDM, ICD | 2015-08-24 10:20 |
Kumamoto | Kumamoto City | Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via Hiroki Shinkawata, Nobuo Tsuboi (REL), Atsushi Tsuda (RSD), Shingo Sato (Kansai), Yasuo Yamaguchi (REL) SDM2015-58 ICD2015-27 |
We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting ar... [more] | SDM2015-58 ICD2015-27 pp.7-10 |
| ICD | 2015-04-16 13:25 |
Nagano | [Invited Lecture]
A 512-kb 1-GHz 28-nm Partially Write Assisted Dual-Port SRAM with Self Adjustable Negative Bias Bitline Shinji Tanaka (Renesas Electronics), Yuichiro Ishii, Makoto Yabuuchi (Renesas), Toshiaki Sano (Renesas System Design), Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato (Renesas) ICD2015-2 |
[more] | ICD2015-2 pp.5-8 |
|
| ICD | 2012-12-17 14:20 |
Tokyo | Tokyo Tech Front | A 250Msps, 0.5W eDRAM-based Search Engine applying full-route capacity dedicated FIB application Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto (Renesas), Koji Yamamoto (RDC), kazunari Inoue (Nara National College of Tech./Osaka Univ.) ICD2012-91 |
[more] | ICD2012-91 pp.21-26 |
| NS, IN (Joint) |
2012-03-09 14:10 |
Miyazaki | Miyazaki Seagia | A Memory Controller with Guaranteed-Bandwidth Solution Hisashi Iwamoto, Yasuto Kuroda, Yuji Yano (Renesas), Koji Yamamoto (RDC), Shingo Ata (Osaka City Univ.), kazunari Inoue (Nara National College of Tec./Osaka Univ.) NS2011-258 |
Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks requi... [more] | NS2011-258 pp.445-450 |
| SDM, ICD | 2011-08-26 15:05 |
Toyama | Toyama kenminkaikan | A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) SDM2011-92 ICD2011-60 |
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bi... [more] | SDM2011-92 ICD2011-60 pp.109-114 |
| ICD, ITE-IST | 2011-07-22 09:50 |
Hiroshima | Hiroshima Institute of Technology | On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors Jinmyoung Kim (Tokyo Univ.), Toru Nakura (VDEC), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (VDEC) ICD2011-27 |
[more] | ICD2011-27 pp.69-72 |
| NS, ICM, CQ (Joint) |
2010-11-19 13:20 |
Kyoto | Katsura Campus, Kyoto Univ. | Cost Evaluation and Parameter Optimization of the Fast Forwarding Engine using Standard Memory Kazuya Zaitsu (Osaka City Univ.), Koji Yamamoto (Renesas Design), Yasuto Kuroda, Kazunari Inoue (Renesas Electronics), Shingo Ata, Ikuo Oka (Osaka City Univ.) NS2010-101 |
Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on ... [more] |
NS2010-101 pp.75-80 |
| ICD, SDM | 2010-08-26 09:10 |
Hokkaido | Sapporo Center for Gender Equality | On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) SDM2010-124 ICD2010-39 |
This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitanc... [more] | SDM2010-124 ICD2010-39 pp.1-4 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | A Multi-Color Space Conversion for Video Input Output Engine Hai Vu Nguyen, Thang Minh Le (RVC), Toyokazu Hori (REL) |
A Mutli-Color Space Conversion (CSC) in Video Input/ Output engine supports different conversion standards by only one l... [more] | |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Designing an Interrupt Controller for a Multi-core System Liem Tan Pham, Huong Thien Hoang, Phong The Vo, Y Thien Vo (RVC), Masayuki Ito (REL) |
Enhancing design efficiency and overall system performance are important targets and design challenges for a multicore s... [more] | |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Toward a High-Performance & Low-Power Application Processor for Portable Navigation Devices Khoa Dac Tran, Hoa Tan Lu, Cuong Phuc Phan, Quang Hai Phan (RVC), Hiroyuki Kudo, Seiichi Negishi, Mitsuyoshi Yamamoto, Yasushi Okamoto (REL) |
We have developed SH7723, an application processor for PND (portable navigation devices). SH7723 introduces a 720-MIPS S... [more] | |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Three-speed-mode Infrared IP Supporting Single-frame and Multi-frame Operation Modes for Latest IrSimple Protocol Nam Hai Nguyen (RVC), Minoru Uemura, Kaoru Fukada, Yoshihiro Konno (REL) |
We have successfully developed an Infrared IP which integrates three speed modes: 1) Serial Infrared Rate (SIR) up to 11... [more] | |
| NS | 2010-05-21 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Hardware Implementation of Fast Forwarding Engine using Standard Memory and Dedicated Circuit Kazuya Zaitsu (Osaka City Univ.), Koji Yamamoto (Renesas Des.), Yasuto Kuroda, Kazunari Inoue (Renesas Ele.), Shingo Ata, Ikuo Oka (Osaka City Univ.) NS2010-26 |
Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on r... [more] | NS2010-26 pp.59-64 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 14:05 |
Kochi | Kochi City Culture-Plaza | Logic stabilization way of open fault with unsuitable logic
-- Aim in simple diagnosis technology -- Masaru Sanada (Koch Univ. of Tech.), Keishi Hashida (Renesas Design), Taiki Yasutomi (Koch Univ. of Tech.) VLD2009-64 DC2009-51 |
An experiment for stabilization of output logic brought by floating gate fault with unsuitable electric value has been e... [more] | VLD2009-64 DC2009-51 pp.161-166 |
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