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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD [detail] | 2020-03-05 10:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Motor Current Signature Analysis Based On-Line Fault Detection of DC Motor Naoki Osako (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Nagisa Ishiura (Kwansei Gakuin Univ.)  VLD2019-111 HWS2019-84 |
This article presents a method for online detection of DC motors' fault based on current signature analysis. While cu... [more] |
VLD2019-111 HWS2019-84 pp.101-106 |
| RISING (2nd) |
2019-11-27 13:55 |
Tokyo | Fukutake Learning Theater, Hongo Campus, Univ. Tokyo | [Poster Presentation]
TCP Throughput Fairness Improvement by Click Switch Yuto Soma (Kogakuin University), Akihiro Nakao, Shu Yamamoto (The University of Tokyo), Masato Oguch (Ochanomizu University), Aki Kobayashi, Saneyasu Yamaguchi (Kogakuin University) |
Many TCP congestion control algorithms have been proposed. These proposals have raised an issue of TCP fairness. The pro... [more] | |
| SR | 2019-05-31 10:00 |
Tokyo | Tokyo Big Sight | [Technology Exhibit]
QZSS short message SS-CDMA communication system
-- Evaluation of transmitting timing control error -- Hiroshi Oguma, Rei Kawai, Takumi Shimada (NIT, Toyama), Takeshi Asai (Next-Dimension), Mizuki Motoyoshi, Suguru Kameda, Noriharu Suematsu (Tohoku Univ.) SR2019-12 |
We have proposed Spread Spectrum Code Division Multiple Access (SS-CDMA) short message communication using Quasi-Zenith... [more] |
SR2019-12 pp.71-77 |
| VLD, IPSJ-SLDM | 2019-05-15 14:20 |
Tokyo | Ookayama Campus, Tokyo Institute of Technology | Approximate Computing Technique Using Memoization and Simplified Multiplication Yoshinori Ono, Kimiyoshi Usami (SIT) VLD2019-2 |
In embedded systems, approximate computing can strongly promote reduction of execution time and energy consumption in ex... [more] | VLD2019-2 pp.13-18 |
| NS | 2019-04-18 13:50 |
Kagoshima | Tenmonkan Vision Hall | Traffic Prioritization using Data-Plane programmable node Shu Yamamoto, Akihiro Nakao (UTokyo) NS2019-6 |
With the utilization of IoT technologies, various devices are connected to the network. This causes the increase of traf... [more] | NS2019-6 pp.31-36 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 10:15 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | CPSY2018-120 DC2018-102 |
We propose a MPU architecture for PLCs (Programmable Logic Controllers) and its complier. The ideaof the speed-up method... [more] | CPSY2018-120 DC2018-102 pp.333-339 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 10:35 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | CPSY2018-121 DC2018-103 |
We propose a speed-up method for PLCs (Programmable Logic Controllers) by only modifying program codes. Ladder diagram ... [more] |
CPSY2018-121 DC2018-103 pp.341-346 |
| DC | 2019-02-27 11:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Efficient Approach to Recycled FPGA Detection Using WID Variation Modeling Foisal Ahmed, Michihiro Shintani, Michiko Inoue (NAIST) DC2018-77 |
Recycled field programmable gate arrays (FPGAs) make a significant threat to mission critical systems due to their perfo... [more] | DC2018-77 pp.37-42 |
| RECONF | 2018-09-18 14:50 |
Fukuoka | LINE Fukuoka Cafe Space | Data Flow Representation and its Applications to Machine Learning Accelerator Kazuki Nakada (Tsukuba Univ. of Tech.), Keiji Miura (Kwansei Gakuin Univ.) RECONF2018-32 |
Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to r... [more] | RECONF2018-32 pp.73-78 |
| RECONF | 2018-05-25 10:35 |
Tokyo | GATE CITY OHSAKI | Design of an MTJ-Based Multi-Functional Lookup Table Circuit Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu (Tohoku Univ.) RECONF2018-12 |
A multi-functional nonvolatile lookup table (LUT) circuit is described using a magnetic tunnel junction (MTJ) and CMOS h... [more] | RECONF2018-12 pp.59-64 |
| SIS | 2018-03-08 15:25 |
Aichi | Meijo Univ. Tempaku Campus | DNN:-MPC: A Hardware oriented Deep Neural Networks for Model Predictive Control Kentaro Honda, Naoki Iwaya (Kyutech), Teppei Hirotsu, Toshiaki Nakamura, Tatuya Horiguchi (HITACHI), Hakaru Tamukoh (Kyutech) SIS2017-60 |
Model Predictive Control (MPC) is one of the control systems, where it uses "predictive model" to control objects. Howev... [more] | SIS2017-60 pp.17-22 |
| VLD, HWS (Joint) |
2018-02-28 09:55 |
Okinawa | Okinawa Seinen Kaikan | On Memory Size Reduction of Programmable Hardware for Random Forest based Network Intrusion Detection Binbin Xue, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2017-90 |
In our previous research, we proposed dedicated programmable hardware of random forest based NIDSs. In this research, we... [more] | VLD2017-90 pp.7-12 |
| VLD, HWS (Joint) |
2018-03-01 09:50 |
Okinawa | Okinawa Seinen Kaikan | Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (Univ. of Aizu) VLD2017-107 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2017-107 pp.109-114 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 10:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Automatic Conversion from Snort PCRE to Verilog HDL Masahiro Fukuda, Yasushi Inoguchi (JAIST) VLD2017-78 CPSY2017-122 RECONF2017-66 |
In this paper, we present how to automatically convert Snort's PCRE (Perl Compatible Regular Expressions) into Verilog H... [more] | VLD2017-78 CPSY2017-122 RECONF2017-66 pp.95-100 |
| NS | 2018-01-18 14:30 |
Okinawa | Ishigakishi-Shoko-Kaikan | Evaluation of Service Identification Based on Multiple TLS Sessions Clustering Masaki Hara, Shinnosuke Nirasawa (Kogakuin Univ.), Akihiro Nakao (UTokyo), Masato Oguchi (Ochanomizu Univ.), Shu Yamamoto (UTokyo), Saneyasu Yamaguchi (Kogakuin Univ.) NS2017-147 |
Identifying services of the traffic by given IP network flow is essential for various purposes, such as management of Qo... [more] | NS2017-147 pp.17-22 |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | Proposal of high precision skew adjustment method with an on-chip setup time measurement circuit Naoto Kamba, Masaki Ishii, Masahiro Sasaki (SIT) CAS2017-84 ICD2017-72 CPSY2017-81 |
In recent years, clock skew which can be tolerated is reduced because the operating speed of integrated circuits increas... [more] | CAS2017-84 ICD2017-72 CPSY2017-81 p.97 |
| CPSY | 2017-11-19 15:00 |
Aomori | Aomori Tourist Information Center, ASPAM | [Poster Presentation]
A Programmable Analog Calculation Unit based on Support Vector Regression Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2017-55 |
This work explores an architecture of programmable analog circuitry to calculate arbitrary functions with acceptable acc... [more] | CPSY2017-55 pp.27-32 |
| PN | 2017-11-16 10:00 |
Tokyo | Kogakuin Univ. | Design of Address Assignment for Multi-Domain Photonic L2 Network Kodai Yarita (Keio Univ.), Takehiro Sato (Kyoto Univ.), Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) PN2017-32 |
In increasing communication traffic and diversifying services, progress of photonic networks and nodes are required. As ... [more] | PN2017-32 pp.29-34 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 13:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | FPGA Implementation of Pattern Matching of PCRE for NIDS and its Acceleration and Memory Saving Masahiro Fukuda, Yasushi Inoguchi (JAIST) RECONF2017-37 |
In this paper, we explain about a development of a tool to automatically generate a circuit for pattern matching of Perl... [more] | RECONF2017-37 pp.1-6 |
| SDM, ICD, ITE-IST [detail] | 2017-08-01 09:45 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | Parallel Programming of Non-volatile Power-up States of SRAM Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya (Univ. of Tokyo), Hirofumi Shinohara (Waseda Univ.), Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2017-38 ICD2017-26 |
A technique for using an ordinary SRAM array for programmable and readable non-volatile (NV) memory is proposed. Paralle... [more] | SDM2017-38 ICD2017-26 pp.49-54 |
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