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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| OCS, OFT, LSJ (Joint) [detail] |
2018-08-30 13:40 |
Hokkaido | Hakodate Hokuyo Building 8Kai Hall | Influence of disturbance on Inter-core Crosstalk between Heterogeneous Cores Yoshimichi Amma, Katsuhiro Takenaga (Fujikura Ltd.), Takeshi Fujisawa, Kunimasa Saitoh, Masanori Koshiba (Hokkaido Univ.), Kazuhiko Aikawa (Fujikura Ltd.)  OCS2018-20 |
A heterogeneous multi-core fiber (MCF) is one of the techniques to reduce inter-core crosstalk (XT) in a MCF. However, t... [more] | OCS2018-20 pp.7-10 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 13:30 |
Kanagawa | Hiyoshi Campus, Keio Univ. | Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops Yuki Kikuchi, Kanemitsu Ootsu, Takanobu Baba, Takashi Yokota, Takeshi Ohkawa (Utsunomiya Univ.) VLD2016-85 CPSY2016-121 RECONF2016-66 |
Recently, heterogeneous multi-core processer is spreading. We should exactly understand both static and dynamic behavio... [more] |
VLD2016-85 CPSY2016-121 RECONF2016-66 pp.103-108 |
| ICD, SDM | 2014-08-04 10:50 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori (Renesas Electronics) SDM2014-64 ICD2014-33 |
This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application pro... [more] | SDM2014-64 ICD2014-33 pp.11-16 |
| RECONF | 2012-05-29 17:35 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Development of Application for Heterogeneous Multi-Core Processor Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.) RECONF2012-16 |
This paper describes the application development on a heterogeneous multi-core processor that consists of a CPU and acce... [more] | RECONF2012-16 pp.89-94 |
| VLD | 2012-03-06 11:00 |
Oita | B-con Plaza | LSI Implementation of Heterogeneous Multi-Chip Processor for energy-saving Embedded Systems : COOL Chip Hiroyuki Uchida, Michiya Hagimoto, Tomoyuki Morimoto, Nobuyuki Hikichi, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Naoya Watanabe, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) VLD2011-122 |
The authors have suggested the low-power embedded heterogeneous multi-chip processor system: COOL Chip. We designed two ... [more] | VLD2011-122 pp.13-17 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-02 15:45 |
Miyagi | Design and implementation of distributed TLB mechanism for heterogeneous multi-core processors Daiki Kawase, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) CPSY2011-84 DC2011-88 |
Heterogeneous multi-core architecture, in which processor cores, memory modules, and I/O modules with various sizes, fu... [more] |
CPSY2011-84 DC2011-88 pp.85-90 |
|
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-02 16:15 |
Miyagi | Design and implementation of I/O control mechanism for heterogeneous multi-core processors Yuki Kawaguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) CPSY2011-85 DC2011-89 |
Heterogeneous multi-core architecture that consists of processors, memory modules, and I/O devices with various sizes, f... [more] | CPSY2011-85 DC2011-89 pp.91-96 |
|
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-03 13:00 |
Miyagi | Development of a FPGA based performance evaluation system for a Ultra-Android prototype Kenji Toda, Osamu Morikawa (AIST), Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Yasumori Hibi, Yukoh Matsumoto (Tops Systems) CPSY2011-91 DC2011-95 |
A performance evaluation system for Ultra-Android platform ,which achieves high performance and less energy consuming an... [more] | CPSY2011-91 DC2011-95 pp.193-198 |
|
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 12:50 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | [Invited Talk]
Heterogeneous Many-Core Application Processor Architecture for Ultra-High-Quality Image Reproduction Yukoh Matsumoto (TOPS) SIP2011-72 ICD2011-75 IE2011-71 |
We have developed CG Application-Domain Specific Heterogeneous Multi-Core architecture and its software for a Desk-Top R... [more] | SIP2011-72 ICD2011-75 IE2011-71 pp.67-71 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:30 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-73 ICD2011-76 IE2011-72 |
Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-... [more] | SIP2011-73 ICD2011-76 IE2011-72 pp.73-76 |
| ICD, IPSJ-ARC | 2011-01-21 11:40 |
Kanagawa | Keio University (Hiyoshi Campus) | Acceleration of Block Matching by using Multiple Alignments on Heterogeneous Multi-Core Processor Yoshitaka Hiramatsu (Hitachi), Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.), Tohru Nojiri, Kunio Uchiyama (Hitachi) |
The large data-transfer time among different cores and data-supply time to arithmetic unit is a big problem in heterogen... [more] | ICD2010-136 pp.57-62 |
| VLD | 2010-09-27 14:25 |
Kyoto | Kyoto Institute of Technology | Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Michitaka Kameyama (Tohoku Univ.) VLD2010-43 |
Heterogeneous multi-core processors are attracted by the media processing applications due to their capability of drawi... [more] |
VLD2010-43 pp.7-12 |
| ICD, SDM | 2007-08-23 08:30 |
Hokkaido | Kitami Institute of Technology | Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Hayato Fujiwara, Kazuya Ishida, Naoto Okumura, Norio Masui, Hiroyuki Kondo (Renesas) SDM2007-141 ICD2007-69 |
A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The co... [more] | SDM2007-141 ICD2007-69 pp.1-4 |
| ICD, SDM | 2007-08-23 09:20 |
Hokkaido | Kitami Institute of Technology | Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71 |
This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] | SDM2007-143 ICD2007-71 pp.11-16 |
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