| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IT, ISEC, WBS | 2019-03-08 16:10 |
Tokyo | University of Electro-Communications | Non-interactive Proof Systems for Group-Dependent Bundled Languages Hiroaki Anada (Univ. of Nagasaki)  IT2018-114 ISEC2018-120 WBS2018-115 |
In this report, we propose a bundled language for the direct product of group-dependent languages. Then we construct... [more] |
IT2018-114 ISEC2018-120 WBS2018-115 pp.243-248 |
| ED, MW | 2014-01-16 12:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Correlation of On-Wafer 400V Dynamic Behavior and Trap Characteristics of GaN-HEMTs Tadahiro Imada, Toshihide Kikkawa (Fujitsu Labs), Daniel Piedra, Tomas Palacios (Massachusetts Inst. of Tech.) ED2013-117 MW2013-182 |
A method for identifying the critical traps regarding to the dynamic behavior of gallium nitride high electron mobility ... [more] | ED2013-117 MW2013-182 pp.41-45 |
| SDM | 2012-11-15 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg | New design method for power devices using topology optimization based on the adjoint variable method Katsuya Nomura, Tsuguo Kondoh, Tsuyoshi Ishikawa, Atsushi Kawamoto, Tadayoshi Matsumori, Takahide Sugiyama (TCRDL) SDM2012-101 |
This study attempt to apply topology optimization to power devices design. We formulated the optimization problem to imp... [more] | SDM2012-101 pp.11-14 |
| SDM, ED (Workshop) |
2012-06-27 11:15 |
Okinawa | Okinawa Seinen-kaikan | Optimization and characterization of 600V super junction power MOSFET using a deep trench structure Yong Tae Kim (KIST), Eun Sik Jung (Maplesemiconductor Inc.), Ey Goo Kang (Far East Univ.) |
Recently, Power MOSFET has been intensively investigated as voltage-driven devices for the applications of large power s... [more] | |
| MW, ED | 2011-01-14 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | AlGaN/GaN HFETs using highly C-doped layers on Si substrate Takuya Kokawa, Syusuke Kaya, Nariaki Ikeda, Sadahiro Kato (APD) ED2010-185 MW2010-145 |
In this paper, AlGaN/GaN/HFET devices on Si substrates were fabricated, and the device characteristics were examined. In... [more] | ED2010-185 MW2010-145 pp.55-59 |
| ICD, ITE-IST | 2009-10-02 10:00 |
Tokyo | CIC Tokyo (Tamachi) | Thermal Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuits Dong Ta Ngoc Huy, Masaya Miyahara, Akira Matsuzawa (Tokyo Inst. of Tech.) ICD2009-48 |
Switch thermal noise represents a major limitation on the performance of switched-capacitor circuits. In these circuits,... [more] | ICD2009-48 pp.81-86 |
| CPM, ED, SDM | 2008-05-16 10:50 |
Aichi | Nagoya Institute of Technology | On-resistance and Breakdown Voltage of Enhancement-Mode AlGaN/GaN Junction HFET Using p-GaN Gate Contact Ryohei Nega, Katsutoshi Mizuno, Motoaki Iwaya, Satoshi Kamiyama, Hiroshi Amano, Isamu Akasaki (Meijo Univ.) ED2008-13 CPM2008-21 SDM2008-33 |
This paper reports normally-off mode nitride-based field-effect transistor using p-type gate contact. In order to realiz... [more] | ED2008-13 CPM2008-21 SDM2008-33 pp.61-66 |
[Return to Top Page]