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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-13 15:25 |
Ehime | Ehime Prefecture Gender Equality Center | Design of Reference-free CMOS Temperature Sensor with Statistical MOSFET Selection Shogo Harada, Mahfuzul Islam, Takashi Hisakado, Osami Wada (Kyoto Univ.)  VLD2019-34 DC2019-58 |
The need for low power temperature sensors that can operate under limited power supply has been increasing. One of the... [more] |
VLD2019-34 DC2019-58 pp.51-56 |
| SDM, ICD, ITE-IST [detail] | 2019-08-09 10:15 |
Hokkaido | Hokkaido Univ., Graduate School /Faculty of Information Science and | Fabrication and electrical characteristics of amorphous-ZnSnO/Si bilayer tunnel FETs Kimihiko Kato (Univ. of Tokyo/AIST), Hiroaki Matsui, Hitoshi Tabata, Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo) SDM2019-46 ICD2019-11 |
We have examined impact of an amorphous ZnSnO channel layer with high thickness uniformity on electrical characteristics... [more] | SDM2019-46 ICD2019-11 pp.63-66 |
| SIP, IT, RCS | 2018-01-22 16:45 |
Kagawa | Sunport Hall Takamatsu | [Invited Talk]
Stochastic resonance and its applicability to communication systems Takaya Yamazato (Nagoya Univ.), Yukihiro Tadokoro, Hiroya Tanaka (Toyota Central R&D Labs.,), Hiroya Tanaka (Nagoya Univ.), Shintaro Arai (Okayama Univ of Science), Yasuo Nakashima, Shintaro Hiraoka (Nagoya Univ.) IT2017-83 SIP2017-91 RCS2017-297 |
Stochastic resonance (SR) is a nonlinear phenomenon where system response can be boosted by adding noise. Traditionally... [more] |
IT2017-83 SIP2017-91 RCS2017-297 pp.167-174 |
| ICD | 2017-04-21 10:00 |
Tokyo | [Invited Lecture]
A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic Harsh N. Patel, Abhishek Roy, Farah B. Yahya, Ningxi Liu, Benton Calhoun (UVA), Akihiko Harada (FEA), Kazuyuki Kumeno, Makoto Yasuda, Taiji Ema (MIFS) ICD2017-11 |
This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology. The 6T SRAM array ... [more] | ICD2017-11 pp.57-61 |
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| VLD | 2017-03-02 09:25 |
Okinawa | Okinawa Seinen Kaikan | FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration Naoyuki Miyagawa, Tomoya Kimura, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2016-109 |
In this paper, we propose Fishbone-in-Cage Capacitor (FiCC) that is a new variant of metal fringe capacitor (MFC), and s... [more] | VLD2016-109 pp.43-47 |
| VLD | 2016-03-01 17:30 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2015-131 |
A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchrono... [more] | VLD2015-131 p.117 |
| ICD, ITE-IST | 2015-07-03 14:20 |
Kanagawa | National Defense Academy | [Invited Talk]
Circuit Design Techniques for Low Power Energy Harvesting System
-- Efficient DC-DC Boost Converter and Ultra-Low Power Digital Circuits -- Mitsuji Okada, Yuzuru Shizuku, Tetsuya Hirose (Kobe Univ.) ICD2015-22 |
In this paper, we present the circuit design techniques for an efficient DC-DC boost converter, a MPPT (Maximum Power Po... [more] | ICD2015-22 pp.47-52 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | High speed design of sub-threshold circuit by using DTMOS Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) VLD2014-88 DC2014-42 |
Low power consumption is achieved by operating circuits in sub-threshold region. However, in sub-threshold region, the... [more] |
VLD2014-88 DC2014-42 pp.117-121 |
| ED | 2014-08-01 11:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. B3-1 | The Theoretical Characteristic and its Experimental Verification of GaAsSb/InGaAs Double-Gate Tunnel FET Kazumi Ohashi, Motohiko Fujimatsu, Yasuyuki Miyamoto (Tokyo Inst. of Tech.) ED2014-54 |
Tunnel FETs are attracted candidates as switching devices for the next generation. In the Tunnel FETs, steep Sub-thresho... [more] | ED2014-54 pp.7-11 |
| CAS, NLP | 2013-09-27 13:10 |
Gifu | Satellite Campus, Gifu University | Operation Verification of Adiabatic Logic in Subthreshold Region Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ) CAS2013-50 NLP2013-62 |
Our previously proposed ultra low-power sub-threshold adiabatic logic has been a problem that noise margin is reduced, s... [more] | CAS2013-50 NLP2013-62 pp.77-82 |
| ICD, SDM | 2012-08-02 11:25 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | [Invited Talk]
Low Energy Dissipation Circuits with 0.5V Operation Voltage and Applications Hirofumi Shinohara (STARC) SDM2012-67 ICD2012-35 |
Extremely low voltage operation down to nearly or less than 0.5V has been gathering attention as a fundamental way to re... [more] | SDM2012-67 ICD2012-35 pp.23-28 |
| ICD | 2010-12-17 13:50 |
Tokyo | RCAST, Univ. of Tokyo | Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems Yu Pu, Xin Zhang, Jim Huang (Univ. of Tokyo), Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) ICD2010-122 |
Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit te... [more] | ICD2010-122 pp.135-140 |
| VLD | 2009-03-13 14:50 |
Okinawa | Study of high-speed low-power system LSI for sub-threshold operation Makoto Tsurukubo, Shigeyoshi Watanabe (Shonan Inst. of Tech Graduate school) VLD2008-166 |
The effect of a basic inverter circuit that applied the DTMOS operation method to the Sub-threshold operation area by us... [more] | VLD2008-166 pp.237-241 |
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| ICD, VLD | 2006-03-10 09:15 |
Okinawa | Low Power Design of System LSI in the Presence of Leakage Current of MOSFET Shigeyoshi Watanabe (Shonan Inst. of Tech.) |
Low power design of system LSI in the presence of leakage current has been described. By using parallel processing archi... [more] | VLD2005-122 ICD2005-239 pp.1-6 |
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