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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 30  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2016-03-01
11:20		 Okinawa Okinawa Seinen Kaikan Timing-error-tolerant AES Cipher
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-123		 With the technologies advance, the importance of crypto circuits is increasing as well. AES cipher is well known as theo... [more] VLD2015-123
pp.73-78
VLD 2016-03-01
11:45		 Okinawa Okinawa Seinen Kaikan In-situ Hardware-Trojan Authentication for Invalidating Malicious Functions
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-124		  [more] VLD2015-124
pp.79-84
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-02
15:55		 Nagasaki Nagasaki Kinro Fukushi Kaikan A low-power soft error tolerant latch scheme on 15nm process
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2015-56 DC2015-52		 In recent technology scaling, reliability of integrated circuits due to a soft error is becoming more critical than ever... [more] VLD2015-56 DC2015-52
pp.123-127
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
10:10		 Nagasaki Nagasaki Kinro Fukushi Kaikan A Quantitative Criterion of Gate-Level Netlist Vulnerability
Masaru Oya, Youhua Shi (Waseda Univ.), Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-59 DC2015-55		 Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry.
This circumstance intr... [more]		 VLD2015-59 DC2015-55
pp.141-146
VLD, IPSJ-SLDM 2015-05-14
15:25		 Fukuoka Kitakyushu International Conference Center AES Encryption Circuit against Clock Glitch based Fault Analysis
Daisuke Hirano, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ) VLD2015-7		 Recently, fault analysis has attracted a lot of attentions as a new kind of side channel attack methods,in which malicio... [more] VLD2015-7
pp.51-55
VLD 2015-03-03
09:15		 Okinawa Okinawa Seinen Kaikan A low-power soft error tolerant latch scheme
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2014-162		 In recent technology scaling, reduction of reliability by soft-error and increase power has appeared as an inevitable pr... [more] VLD2014-162
pp.55-60
VLD 2015-03-04
13:25		 Okinawa Okinawa Seinen Kaikan A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-182		 Recently, digital ICs are designed by outside vendors to reduce costs
in semiconductor industry. This circumstance intr... [more]		 VLD2014-182
pp.165-170
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
10:50		 Kanagawa Hiyoshi Campus, Keio University A Hardware Trojan Detection Method based on Trojan net features
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-137 CPSY2014-146 RECONF2014-70		 Recently, digital ICs are designed by outside vendors to reduce costs
in semiconductor industry. This circumstance intr... [more]		 VLD2014-137 CPSY2014-146 RECONF2014-70
pp.157-162
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
09:15		 Oita B-ConPlaza Design of Flip-Flop with Timing Error Tolerance
Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33		 Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] VLD2014-79 DC2014-33
pp.45-50
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
09:40		 Oita B-ConPlaza Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits
Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34		 The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] VLD2014-80 DC2014-34
pp.51-56
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
10:05		 Oita B-ConPlaza An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-81 DC2014-35		 As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error cor... [more] VLD2014-81 DC2014-35
pp.57-62
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
16:15		 Oita B-ConPlaza High speed design of sub-threshold circuit by using DTMOS
Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) VLD2014-88 DC2014-42		 Low power consumption is achieved by operating circuits in sub-threshold region.
However, in sub-threshold region, the... [more]		 VLD2014-88 DC2014-42
pp.117-121
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-26
17:30		 Oita B-ConPlaza A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-91 DC2014-45		 Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry.
This circumstan... [more]		 VLD2014-91 DC2014-45
pp.135-140
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2014-11-28
15:35		 Oita B-ConPlaza Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56		 An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] VLD2014-102 DC2014-56
pp.203-208
IE, ICD, VLD, IPSJ-SLDM [detail] 2014-10-02
13:25		 Miyagi   Local pulse generation in variable stages pipeline designs for low energy consumption
Takayuki Nii, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Univ.), Masao Yanagisawa (Waseda Univ.) VLD2014-61 ICD2014-54 IE2014-40		 The increase of energy consumption due to improved performance has become a problem in the mobile terminal, and various ... [more] VLD2014-61 ICD2014-54 IE2014-40
pp.7-12
VLD 2014-03-03
16:00		 Okinawa Okinawa Seinen Kaikan Latch-based AES Encryption Circuit Against Fault Analysis
Youhua Shi, Hiroaki Taniguchi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2013-140		 In general, cryptography is considered to be secure because it is based on complicated mathematical theories. In recent ... [more] VLD2013-140
pp.37-42
VLD 2014-03-03
16:25		 Okinawa Okinawa Seinen Kaikan Secure scan design using improved random order scans and its evaluations
Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-141		 Scan test using scan chains is one of the most important DFT techniques.
On the other hand, scan-based attacks are repo... [more]		 VLD2013-141
pp.43-48
VLD 2014-03-05
13:25		 Okinawa Okinawa Seinen Kaikan Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits
Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.) VLD2013-161		 Low voltage design has been used in order to reduce the energy dissipation of mobile network equipment. However, as supp... [more] VLD2013-161
pp.147-151
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-27
14:55		 Kagoshima   Suspicious timing error prediction using check points
Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-67 DC2013-33		 Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error ... [more] VLD2013-67 DC2013-33
pp.39-44
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
11:40		 Kagoshima   Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-97 DC2013-63		 In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture.
In HDR-mcd,... [more]		 VLD2013-97 DC2013-63
pp.263-268
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