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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 12 of 12  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2019-02-28
14:55		 Okinawa Okinawa Ken Seinen Kaikan [Memorial Lecture] Methods for Reducing Power and Area of BDD-based Optical Logic Circuits
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.), Akihiko Shinya, Masaya Notomi (NTT) VLD2018-116 HWS2018-79		  [more] VLD2018-116 HWS2018-79
pp.139-144
VLD, HWS
(Joint)		 2018-03-02
11:20		 Okinawa Okinawa Seinen Kaikan Energy Reduction of Standard-Cell Memory Exploiting Selective Activation
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2017-124		 On-chip memories have a large impact on energy-efficiency of LSI circuits. This paper discusses energy-efficient on-chip... [more] VLD2017-124
pp.211-216
CAS, CS 2017-02-23
16:05		 Shiga   [Invited Talk] CMOS Optical Receiver for High Density and High Speed Optical Interconnection
Akira Tsuchiya, Takuya Nakao (Kyoto Unv.), Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka (NTT), Hidetoshi Onodera (Kyoto Unv.) CAS2016-124 CS2016-85		  [more] CAS2016-124 CS2016-85
pp.59-62
SDM 2017-02-06
14:10		 Tokyo Tokyo Univ. [Invited Talk] Large Scale Crossbar Switch Block (CSB) with Via-Switch for a Low-Power FPGA
Naoki Banno, Munehiro Tada, Koichiro Okamoto, Noriyuki Iguchi, Toshitsugu Sakamoto, Hiromitsu Hada (NEC Corp.), Hiroyuki Ochi (Ritsumeikan Univ.), Hidetoshi Onodera (Kyoto Univ.), Masanori Hashimoto (Osaka Univ.), Tadahiko Sugibayashi (NEC Corp.) SDM2016-144		  [more] SDM2016-144
pp.29-34
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]		 2016-11-28
15:30		 Osaka Ritsumeikan University, Osaka Ibaraki Campus Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process
Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.) VLD2016-52 DC2016-46		 We propose a circuit analysis method using the bimodal RTN (random telegraph
noise) model of the defect-centric distri... [more]		 VLD2016-52 DC2016-46
pp.49-54
ICD, MW 2016-03-04
10:50		 Hiroshima Hiroshima University [Invited Talk] Design Challenges and Solutions in the era of IoT
Hidetoshi Onodera (Kyoto Univ.) MW2015-206 ICD2015-129		 The talk stars by the exploration of integrated circuits in the era of IoT predicted by empirical laws that have been co... [more] MW2015-206 ICD2015-129
p.187
ICD, MW 2016-03-04
15:35		 Hiroshima Hiroshima University Bandwidth Enhancement of Regulated Cascode Transimpedance Amplifier using Inverter Amplifier Stage
Masamichi Fujiwara, Akira Tsuchiya (Kyoto Univ.), Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka (NTT), Hidetoshi Onodera (Kyoto Univ.) MW2015-214 ICD2015-137		  [more] MW2015-214 ICD2015-137
pp.229-233
VLD 2016-03-01
17:30		 Okinawa Okinawa Seinen Kaikan [Memorial Lecture] A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2015-131		 A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchrono... [more] VLD2015-131
p.117
ICD, CPSY 2015-12-17
09:40		 Kyoto Kyoto Institute of Technology RTN Modeling of Ring Oscillators by a Bimodal Defect-Centric Behavior in a 40 nm process
Azusa Oshima (KIT), Pieter Weckx, Ben Kaczer (IMEC), Takashi Matsumoto (UT), Kazutoshi Kobayash (KIT), Hidetoshi Onodera (KU) ICD2015-63 CPSY2015-76		  [more] ICD2015-63 CPSY2015-76
pp.1-6
ICD, CPSY 2015-12-17
16:00		 Kyoto Kyoto Institute of Technology [Poster Presentation] RTN Modeling of Ring Oscillators by a Bimodal Defect-Centric Behavior in a 40 nm process
Azusa Oshima (KIT), Pieter Weckx, Ben Kaczer (IMEC), Takashi Matsumoto (UT), Kazutoshi Kobayashi (KIT), Hidetoshi Onodera (KU) 		 [more]
DC, CPSY 2015-04-17
13:25		 Tokyo   A study of processor architecture suited for intelligent sensing system
Hiroki Hihara, Akira Iwasaki (Univ. of Tokyo), Masanori Hashimoto (Osaka Univ./JST CREST), Hiroyuki Ochi (Rits/JST CREST), Yukio Mitsuyama (KUT/JST CREST), Hidetoshi Onodera (Kyoto Univ./JST CREST), Hiroyuki Kanbara (ASTEM/JST CREST), Kazutoshi Wakabayashi, Takashi Takenaka, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada (NEC/JST CREST) CPSY2015-8 DC2015-8		 Sensor nodes are now important elements for the system of social infrastructure, and thus intelligent processing capabil... [more] CPSY2015-8 DC2015-8
pp.43-48
VLD 2015-03-03
15:50		 Okinawa Okinawa Seinen Kaikan [Memorial Lecture] Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2014-172		 Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of micropro... [more] VLD2014-172
pp.109-114
 Results 1 - 12 of 12  /   
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