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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NLP, MSS | 2025-03-14 18:00 |
Okinawa | Miyakojima City Central Community Center (Okinawa) | Distributed Online Proximal Gradient Method over Open Networks Masahiro Iida, Naoki Hayashi, Masahiro Inuiguchi (Osaka Univ.) |
[more] | |
| VLD, RECONF | 2025-01-17 13:55 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Introduction and Evaluation of a Programmable Buffer for Stencil Computation on RIKEN CGRA Takumi Okada, Yasunori Osana, Masahiro Iida (Kumamoto Univ.), Boma Adhi, Kentaro Sano (R-CCS), Omar Ragheb, Jason Anderson (UofT)  VLD2024-95 RECONF2024-125 |
Stencil computation is critical in many scientific and technological fields, including numerical simulation and image pr... [more] | VLD2024-95 RECONF2024-125 pp.104-109 |
| VLD, RECONF | 2025-01-17 15:10 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Proposal and evaluation of Heterostructure Clusters Using PAE Cells for eFPGA IP Tatsuya Sasaki, Ryo Iwasaki, Kensyu Seto, Masahiro Iida (Kumamoto Univ.) VLD2024-98 RECONF2024-128 |
We are currently proposing a new logic cell called the PAE Cell as a replacement for LUTs (Look-Up Tables) in eFPGA IP. ... [more] | VLD2024-98 RECONF2024-128 pp.122-127 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-12 14:55 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
New Cluster Architecture and Clustering Method Using PAE Cells for eFPGA IP Ryo Iwasaki, Tatsuya Sasaki, Kenshu Seto, Masahiro Iida (Kumamoto Univ) VLD2024-30 ICD2024-48 DC2024-52 RECONF2024-60 |
[more] | VLD2024-30 ICD2024-48 DC2024-52 RECONF2024-60 pp.20-25 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-14 09:25 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Proposal for NV of Logic Cell Architecture for eFPGA IP Keizo Hiraga (SSS), Kensu Seto, Masahiro Iida (Kumamoto Univ), Kazuhiro Bessho (SSS) VLD2024-63 ICD2024-81 DC2024-85 RECONF2024-93 |
As eFPGAs (embedded FPGAs) are required to shift from hard IP to soft IP, we propose to make a new programmable logic ce... [more] | VLD2024-63 ICD2024-81 DC2024-85 RECONF2024-93 pp.204-209 |
| NC, MBE (Joint) |
2024-09-27 14:50 |
Miyagi | Tohoku Univ. (Miyagi, Online) (Primary: On-site, Secondary: Online) |
Lightweight computation in inference of SNN models for LSI Kei Sakamoto, Yuhei Kobayashi, Hiroto Kitani, Masahiro Iida (Kumamoto Univ) NC2024-35 |
Spiking neural networks (SNNs), which closely mimic the human brain, are currently attracting attention due to their hig... [more] | NC2024-35 pp.17-22 |
| NC, MBE (Joint) |
2024-09-27 15:15 |
Miyagi | Tohoku Univ. (Miyagi, Online) (Primary: On-site, Secondary: Online) |
Evaluation of lightweight methods for SNN models using sound source localisation task Hiroto Kitani, Kei Sakamoto, Masahiro Iida (Kumamoto Univ) NC2024-36 |
Spiking neural networks (SNNs), which mimic the neural activity of the brain, are used in biological research to elucida... [more] | NC2024-36 pp.23-28 |
| RECONF | 2024-09-17 14:30 |
Niigata | (Niigata, Online) (Primary: On-site, Secondary: Online) |
Performance Evaluation of eFPGA Using a New Programmable Logic Element: PAE Cell Ryo Iwasaki, Tatsuya Sasaki, Kenshu Seto, Masahiro Iida (Kumamoto Univ.) RECONF2024-45 |
[more] | RECONF2024-45 pp.18-23 |
| RECONF | 2024-09-18 14:15 |
Niigata | (Niigata, Online) (Primary: On-site, Secondary: Online) |
Shell-Role style FPGA chip SLMLET-2 for IoT applications Hideharu Amano, Takuya Kojima (U. Tokyo), Morihiro Kuga (Kumamoto Univ.), Hayate Okuhara (NUS), Masahiro Iida (Kumamoto Univ.) RECONF2024-54 |
In recent years, efforts have been underway to enhance the functionality and performance of IoT edge devices, aiming to ... [more] | RECONF2024-54 pp.60-65 |
| RECONF | 2024-09-18 14:40 |
Niigata | (Niigata, Online) (Primary: On-site, Secondary: Online) |
Development of improved eFPGA-IP for MEC devices Zhan Yan, Koudai Takeno, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) RECONF2024-55 |
The authors are developing an FPGA (Field Programmable Gate Array)-IP for MEC (Multi-access Edge Computing) devices, whi... [more] | RECONF2024-55 pp.66-71 |
| RECONF | 2024-09-18 15:05 |
Niigata | (Niigata, Online) (Primary: On-site, Secondary: Online) |
Consideration of floorplan of DSP block in FPGA-IP for MEC device Kodai Takeno, Zhan Yan, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) RECONF2024-56 |
The authors are developing FPGA-IP to be embedded in chips as part of their research on MEC (Multi-access Edge Computing... [more] | RECONF2024-56 pp.72-78 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-17 14:10 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Kumamoto, Online) (Primary: On-site, Secondary: Online) |
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic Souhei Takagi, Takuya Kozima, Hideharu Amano (Keio Univ), Morihiro Kuga, Masahiro Iida (Kumamoto Univ) VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 |
SLM (Scalable Logic Module) is a fine-grained reconfigurable logic developed by Kumamoto University, characterized by it... [more] | VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 pp.215-220 |
| RECONF | 2023-09-15 14:15 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Tokyo, Online) (Primary: On-site, Secondary: Online) |
Library Development for RISC-V FPGA SoCs Takuya Kojima (UTokyo/JST PRESTO), Yosuke Yanai (Keio Univ.), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) RECONF2023-31 |
[more] | RECONF2023-31 pp.52-57 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-04 18:20 |
Hokkaido | Hakodate Arena (Hokkaido, Online) (Primary: On-site, Secondary: Online) |
Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ./JST PRESTO), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) CPSY2023-25 DC2023-25 |
In recent years, opportunities requiring processing at the IoT edge have been increasing. As a solution, not only conven... [more] | CPSY2023-25 DC2023-25 pp.100-105 |
| NC, NLP | 2023-01-29 13:35 |
Hokkaido | Future University Hakodate (Hokkaido, Online) (Primary: On-site, Secondary: Online) |
Evaluation of SNN simulator SULI for LSI development Yujiro Kozaki, Kei Sakamoto, Masahiro Iida (Kumamoto Univ) NLP2022-101 NC2022-85 |
[more] | NLP2022-101 NC2022-85 pp.107-111 |
| RECONF | 2022-09-08 09:45 |
Aichi | emCAMPUS STUDIO (Aichi, Online) (Primary: On-site, Secondary: Online) |
FPGA implementation of small area sum-of-products arithmetic unit for Posit and consideration of its introduction into AI chip ReNA Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) RECONF2022-33 |
[more] | RECONF2022-33 pp.23-28 |
| RECONF | 2022-09-08 10:10 |
Aichi | emCAMPUS STUDIO (Aichi, Online) (Primary: On-site, Secondary: Online) |
Proposal and evaluation of Combined Posit MAC unit (CPMAC) for both DNN inference and training Yuta Masuda, Yasuhiro Nakahara, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) RECONF2022-34 |
Recently, there has been a lot of research on DNN hardware accelerators for the edge that use Posit as a number represen... [more] | RECONF2022-34 pp.29-34 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 13:30 |
Yamaguchi | Kaikyo Messe Shimonoseki (Yamaguchi, Online) (Primary: On-site, Secondary: Online) |
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8 |
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] | CPSY2022-8 DC2022-8 pp.41-46 |
| RECONF | 2022-06-07 16:45 |
Ibaraki | CCS, Univ. of Tsukuba (Ibaraki, Online) (Primary: On-site, Secondary: Online) |
Preliminary Evaluation of FPGA-to-FPGA Communication Speed in FPGA Cluster ESSPER Rintaro Sakai, Yasuhiro Nakahara (Kumamoto Univ. /R-CSS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CSS) RECONF2022-11 |
This study evaluates the communication speed between FPGAs assuming the FPGA cluster ESSPER is a scalable and flexible ... [more] |
RECONF2022-11 pp.48-49 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 14:30 |
Online | Online (Online) | Compression of configuration data in Scalable Logic Module Souhei Takagi, Naoya Niwa, Yoshiya Shikama, Yosuke Yanai, Hideharu Amano (Keio Univ), Yuya Nakasato, Daiki Amagasaki, Masahiro Iida (Kumamoto Univ) CPSY2021-49 DC2021-83 |
(To be available after the conference date) [more] | CPSY2021-49 DC2021-83 pp.26-31 |
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