| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NC, MBE (Joint) |
2024-09-27 14:50 |
Miyagi | Tohoku Univ. (Primary: On-site, Secondary: Online) |
Reduction of computational complexity of SNN inference for LSI Kei Sakamoto, Yuhei Kobayashi, Hiroto Kitani, Masahiro Iida (Kumamoto Univ) |
[more] | |
| NC, MBE (Joint) |
2024-09-27 15:15 |
Miyagi | Tohoku Univ. (Primary: On-site, Secondary: Online) |
Evaluation of lightweight methods for SNN models using sound source localisation task Hiroto Kitani, Kei Sakamoto, Masahiro Iida (Kumamoto Univ) |
[more] | |
| RECONF | 2024-09-17 14:30 |
Niigata | (Primary: On-site, Secondary: Online) |
SLMLET-2: a shell-role type FPGA chip for IoT Hideharu Amano, Takuya Kojima (U. Tokyo), Morihiro Kuga (Kumamoto Univ.), Hayate Okuhara (NUS), Masahiro Iida (Kumamoto Univ.) |
[more] | |
| RECONF | 2024-09-17 14:55 |
Niigata | (Primary: On-site, Secondary: Online) |
Consideration of floorplan of DSP block in FPGA-IP for MEC device Kodai Takeno, Zhan Yan, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) |
[more] | |
| RECONF | 2024-09-18 14:15 |
Niigata | (Primary: On-site, Secondary: Online) |
Evaluating eFPGA Performance with the new programmable logic element: PAE Cell Ryo Iwasaki, Tatsuya Sasaki, Kenshu Seto, Masahiro Iida (Kumamoto Univ.) |
[more] | |
| RECONF | 2024-09-18 14:40 |
Niigata | (Primary: On-site, Secondary: Online) |
Development of improved eFPGA-IP for MEC devices Zhan Yan, Koudai Takeno, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) |
[more] | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-17 14:10 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic Souhei Takagi, Takuya Kozima, Hideharu Amano (Keio Univ), Morihiro Kuga, Masahiro Iida (Kumamoto Univ)  VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 |
SLM (Scalable Logic Module) is a fine-grained reconfigurable logic developed by Kumamoto University, characterized by it... [more] | VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 pp.215-220 |
| RECONF | 2023-09-15 14:15 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Library Development for RISC-V FPGA SoCs Takuya Kojima (UTokyo/JST PRESTO), Yosuke Yanai (Keio Univ.), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) RECONF2023-31 |
[more] | RECONF2023-31 pp.52-57 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-04 18:20 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Power Evaluation of "SLMLET" Chip with Mixed RISC-V MP and SLM Reconfiguration Logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ./JST PRESTO), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) CPSY2023-25 DC2023-25 |
In recent years, opportunities requiring processing at the IoT edge have been increasing. As a solution, not only conven... [more] | CPSY2023-25 DC2023-25 pp.100-105 |
| NC, NLP | 2023-01-29 13:35 |
Hokkaido | Future University Hakodate (Primary: On-site, Secondary: Online) |
Evaluation of SNN simulator SULI for LSI development Yujiro Kozaki, Kei Sakamoto, Masahiro Iida (Kumamoto Univ) NLP2022-101 NC2022-85 |
[more] | NLP2022-101 NC2022-85 pp.107-111 |
| RECONF | 2022-09-08 09:45 |
Aichi | emCAMPUS STUDIO (Primary: On-site, Secondary: Online) |
FPGA implementation of small area sum-of-products arithmetic unit for Posit and consideration of its introduction into AI chip ReNA Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) RECONF2022-33 |
[more] | RECONF2022-33 pp.23-28 |
| RECONF | 2022-09-08 10:10 |
Aichi | emCAMPUS STUDIO (Primary: On-site, Secondary: Online) |
Proposal and evaluation of Combined Posit MAC unit (CPMAC) for both DNN inference and training Yuta Masuda, Yasuhiro Nakahara, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) RECONF2022-34 |
Recently, there has been a lot of research on DNN hardware accelerators for the edge that use Posit as a number represen... [more] | RECONF2022-34 pp.29-34 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 13:30 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8 |
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] | CPSY2022-8 DC2022-8 pp.41-46 |
| RECONF | 2022-06-07 16:45 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Preliminary Evaluation of FPGA-to-FPGA Communication Speed in FPGA Cluster ESSPER Rintaro Sakai, Yasuhiro Nakahara (Kumamoto Univ. /R-CSS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CSS) RECONF2022-11 |
This study evaluates the communication speed between FPGAs assuming the FPGA cluster ESSPER is a scalable and flexible ... [more] |
RECONF2022-11 pp.48-49 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 14:30 |
Online | Online | Compression of configuration data in Scalable Logic Module Souhei Takagi, Naoya Niwa, Yoshiya Shikama, Yosuke Yanai, Hideharu Amano (Keio Univ), Yuya Nakasato, Daiki Amagasaki, Masahiro Iida (Kumamoto Univ) CPSY2021-49 DC2021-83 |
(To be available after the conference date) [more] | CPSY2021-49 DC2021-83 pp.26-31 |
| ICSS, IPSJ-SPT | 2022-03-08 10:00 |
Online | Online | Input predictive attack by keyboard acoustic emanations using BERT and its countermeasures Masahiro Iida (Teikyo Univ.), Mitsuaki Akiyama (NTT), Masaki Kamizono (DTCY), Takahiro Kasama (NICT), Yuichi Hattori (Secure Cycle Inc.), Hiroyuki Inoue (Kyoto Sangyo Univ.), Atsuo Inomata (Osaka Univ.) ICSS2021-67 |
The Keyboard Acoustic Emanations has been proposed to estimate the input key from keystroke sounds as a kind of side-cha... [more] | ICSS2021-67 pp.49-54 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 16:45 |
Online | Online | A study of an accelerator for CNN inference on FPGA clusters Rintaro Sakai (Kumamoto Univ. /R-CSS), Yasuhiro Nakahara (Kumamoto Univ. /R-CCS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CCS) VLD2021-60 CPSY2021-29 RECONF2021-68 |
In this study, we propose a CNN accelerator for FPGA clusters, which accelerates the CNN inference process by distributi... [more] | VLD2021-60 CPSY2021-29 RECONF2021-68 pp.61-66 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 13:15 |
Online | Online | A Study on Technology mapping method for Scalable Logic Module Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.) VLD2021-68 CPSY2021-37 RECONF2021-76 |
The LUT (Lookup Table) , which is widely used as the logic cell in FPGA (Field Programmable Gate Array）, can implement a... [more] | VLD2021-68 CPSY2021-37 RECONF2021-76 pp.108-113 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online | Online | Basic evaluation of ReNA, a DNN accelerator using numerical representation posit Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) VLD2021-24 ICD2021-34 DC2021-30 RECONF2021-32 |
In Convolutional Neural Network (CNN) accelerators for edge, numerical precision of data should be reduced as much as po... [more] | VLD2021-24 ICD2021-34 DC2021-30 RECONF2021-32 pp.43-48 |
| RECONF | 2021-06-08 16:10 |
Online | Online | Automatic generation of executable code for ReNA Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) RECONF2021-6 |
We have been developing ReNA as a CNN accelerator for the edge, which is controlled by directly specifying control signa... [more] | RECONF2021-6 pp.26-31 |
[Return to Top Page]