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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 13 of 13  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ET 2022-03-04
15:45
Online Online Data visualization function in the IoT learning system adapted to the educational needs
Takaaki Kato, Mizue Kayama (Shinshu Univ.), Takashi Nagai (iot), Yusaku Kanda, Takashi Shimizu (Shinshu Univ.) ET2021-79
We have been developing educational IoT materials for use in classes where experiments with measurement activities are r... [more] ET2021-79
pp.157-162
DC 2022-03-01
10:55
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement
Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT) DC2021-67
It is effective for aging of a logic circuit to measure a circuit delay periodically in field. In order to compare the d... [more] DC2021-67
pp.18-23
ET 2021-03-06
15:40
Online Online A proposal for the Off-line and online IoT based data management system with time series graphs authoring function
Aki Asano, Mizue Kayama (Shinshu Univ.), Takashi Nagai (IoT), Takaaki Kato (Shinshu Univ.) ET2020-74
The purpose of this research is to propose an IoT platform that also supports offline use. To achieve this goal, we desi... [more] ET2020-74
pp.127-132
DC 2020-12-11
13:00
Hyogo
(Primary: On-site, Secondary: Online)
A Degradation Prediction of Circuit Delay Using A Gradient Descent Method
Seiichirou Mori, Masayuki Gondou, Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech) DC2020-59
As the risk of aging-induced faults of VLSIs is increasing, highly reliable systems require to predict when the aging-in... [more] DC2020-59
pp.1-6
DC 2019-12-20
16:30
Wakayama   Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test
Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85
Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] DC2019-85
pp.37-42
PRMU, BioX 2019-03-18
14:45
Tokyo   [Short Paper] A trial on sport-informatics
Junnosuke Kado (Kyushu Univ.), Akinori Nagata (Chukyo Univ.), Takaaki Kato (Keio Univ.), Seiichi Uchida (Kyushu Univ.) BioX2018-63 PRMU2018-167
(To be available after the conference date) [more] BioX2018-63 PRMU2018-167
pp.197-200
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:25
Hiroshima Satellite Campus Hiroshima Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips
Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) VLD2018-57 DC2018-43
Scan-based logic BIST has a crucial problem of high test power dissipation. Its solution requires a flexible test power ... [more] VLD2018-57 DC2018-43
pp.125-130
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:00
Kumamoto Kumamoto-Kenminkouryukan Parea Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST
Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech) VLD2017-41 DC2017-47
A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of f... [more] VLD2017-41 DC2017-47
pp.85-90
DC 2015-12-18
13:20
Niigata Kurieito Mulakami (Murakami City) On Measurement of On-Chip Temperature And Voltage Variation Using A Digital Monitor
Yousuke Miyake, Takaaki Kato, Takuya Itonaga, Yasuo Sato, Seiji Kajihara (KIT) DC2015-74
A digital monitor for measuring a temperature and a voltage of VLSIs is proposed. The monitor can derive measurement res... [more] DC2015-74
pp.5-10
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
09:20
Kagoshima   Design and evaluation of circuits to control scan-in power in logic BIST
Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) VLD2013-93 DC2013-59
Power reduction during Logic BIST is a crucial problem; however, power controlling technologies are required as well as ... [more] VLD2013-93 DC2013-59
pp.233-238
DC 2012-06-22
15:45
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg An Evaluation of Low Power BIST Method
Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara (Kyutech) DC2012-14
Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophi... [more] DC2012-14
pp.33-38
DC 2012-02-13
11:55
Tokyo Kikai-Shinko-Kaikan Bldg. A method to reduce shift-toggle rate for low power BIST
Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) DC2011-80
Logic BIST using scan design has a problem with high power dissipation during test. In this work we propose a method tha... [more] DC2011-80
pp.25-29
MSS 2006-06-01
15:05
Ishikawa Ishikawa Science Park Reachability analysis of probabilistic linear hybrid automaton based on predicate abstraction and its refinement
Takaaki Kato (Kanazawa Univ.), Yosuke Mutsuda (NEC), Satoshi Yamane (Kanazawa Univ.)
As ubiquitous computing has progressed, systems are embedded in widespread environments. Then it is important to guarant... [more] CST2006-4
pp.19-24
 Results 1 - 13 of 13  /   
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