IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 108, Number 412

VLSI Design Technologies

Workshop Date : 2009-01-29 - 2009-01-30 / Issue Date : 2009-01-22

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Table of contents

VLD2008-91
Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction
Toru Sano, Hideharu Amano (Keio Univ)
pp. 1 - 6

VLD2008-92
Evaluation of a Multicore Reconfigurable Architecture
Vu Manh Tuan, Hiroki Matsutani, Naohiro Katsura, Hideharu Amano (Keio Univ.)
pp. 7 - 12

VLD2008-93
Power Reduction of Dynamically Reconfigurable Processor using Dual-Vth Technologies
Keiichiro Hirai, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.)
pp. 13 - 17

VLD2008-94
Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array
Kazuki Sato, Baatarsuren Bars, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.)
pp. 19 - 24

VLD2008-95
FPGA Implementation of Metastability-based True Random Number Generator
Hisashi Hata, Shuichi Ichikawa (TUT)
pp. 25 - 30

VLD2008-96
A Proposal of Message Driven IP Core Interface
Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.)
pp. 31 - 36

VLD2008-97
A programmable 9-contexts optically reconfigurable gate arrays and its writer
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)
pp. 37 - 40

VLD2008-98
Perfect demonstration of a four-context Optically Reconfigurable Gate Array
Takayuki Mabuchi, Minoru Watanabe (Shizuoka Univ.)
pp. 41 - 44

VLD2008-99
Comparison evaluation of an inversion/non-inversion dynamic optically reconfiguration architecture
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.)
pp. 45 - 50

VLD2008-100
Circuit Partition Method with Time-multiplexed I/O
Tatsuki Isomura (Univ. of Kitakyushu), Masato Inagi (Hiroshima City Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC)
pp. 51 - 55

VLD2008-101
An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
pp. 57 - 62

VLD2008-102
A Proposal of the Computer Architecture for Numbers of Arbitrary Word Length
Shohei Hashimoto, Yuta Totsuka, Masamichi Makino, Hikaru Yasuda, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.)
pp. 63 - 68

VLD2008-103
Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core
Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 69 - 74

VLD2008-104
An Experimental Linux Cluster System for Tests
Koichi Kitano (Polytech.Univ.), Koji Teramoto (EHDO), Tadayoshi Horita (Polytech.Univ.)
pp. 75 - 79

VLD2008-105
Extension of High Level Synthesis system CCAP for AMP multi-core system desin
Yoshiyuki Ishimori, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Nagoya Univ.), Hiroyuki Kanbara (ASTEM)
pp. 81 - 86

VLD2008-106
A Tunable LSI Based on Timing Skew and Stall Adjustments
Yayumi Uehara, Mineo Kaneko (JAIST)
pp. 87 - 92

VLD2008-107
Fast Module Placement in Floorplan-aware High-level Synthesis
Wataru Sato, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 93 - 98

VLD2008-108
A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors
Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 99 - 104

VLD2008-109
Automatic Equivalence Specification between Two Sequential Circuits in High-level Design
Jinmei Xu, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (University of Tokyo)
pp. 105 - 110

VLD2008-110
Formal Verification Method for Protocol Transducer Using Automatically Generated Properties from Specification
Fei Gao, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo)
pp. 111 - 116

VLD2008-111
Foreknown Regularity Arithmetic Processing Unit
Jin Sato, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.)
pp. 117 - 122

VLD2008-112
Improvement of Search Efficiency by Principal Component Analysis for Analog Circuit Sizing of Operational Amplifier using Genetic Algorithm
Yuji Takehara (Toyohashi Univ. Tech.), Masanori Natsui (Tohoku Univ.), Yoshiaki Tadokoro (Toyohashi Univ. Tech.)
pp. 123 - 128

VLD2008-113
A study for accurate RTL timing modeling
Shota Nakajima, Masahiro Fukui (Ritsumeikan Univ.)
pp. 129 - 134

VLD2008-114
Interaction of Abstraction Processing for Creation of Ideas -- An Electronic Brain like a thought of human being --
Tadayuki Hattori
pp. 135 - 140

VLD2008-115
A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems
Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT)
pp. 141 - 146

VLD2008-116
A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 147 - 152

VLD2008-117
Combine operation pattern extraction from CDFG for DSP generation
Toshiyuki Kato, Takaaki Miyake, Shinichi Oomata, Hideto Nishikado, Hironori Yamauchi (Ritsumei Univ), Shiro Kobayashi (Asahi Kasei)
pp. 153 - 158

VLD2008-118
Customizing of Domain-Specific and Compact Reconfigurable HW
Shogo Nakaya, Nobuki Kajihara, Toru Awashima (NEC)
pp. 159 - 164

VLD2008-119
Delay Evaluation of 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation
Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ.)
pp. 165 - 170

VLD2008-120
Implementation of Asynchronous Bus for GALS System
Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.)
pp. 171 - 176

VLD2008-121
A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application
Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 177 - 182

VLD2008-122
Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA
Masaru Kato, Toru Sano, Hideharu Amano (Keio Univ)
pp. 183 - 188

VLD2008-123
An Architecture of Regular Expression Matching Machine for NIDS and Its FPGA Implementation
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ)
pp. 189 - 194

VLD2008-124
An FPGA implementation of Gibbs sampling method towards high-speed motif search
Yuka Sato, Junko Tazawa, Toshiaki Miyazaki (Univ. of Aizu)
pp. 195 - 199

VLD2008-125
Fast Solution of Link Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2
Taku Kihara, Sho Shimizu, Shan Gao, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Akifumi Watanabe (IPFlex)
pp. 201 - 206

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan