Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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CPSY2008-53
Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction
Toru Sano, Hideharu Amano (Keio Univ)
pp. 1 - 6
CPSY2008-54
Evaluation of a Multicore Reconfigurable Architecture
Vu Manh Tuan, Hiroki Matsutani, Naohiro Katsura, Hideharu Amano (Keio Univ.)
pp. 7 - 12
CPSY2008-55
Power Reduction of Dynamically Reconfigurable Processor using Dual-Vth Technologies
Keiichiro Hirai, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.)
pp. 13 - 17
CPSY2008-56
Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array
Kazuki Sato, Baatarsuren Bars, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.)
pp. 19 - 24
CPSY2008-57
FPGA Implementation of Metastability-based True Random Number Generator
Hisashi Hata, Shuichi Ichikawa (TUT)
pp. 25 - 30
CPSY2008-58
A Proposal of Message Driven IP Core Interface
Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.)
pp. 31 - 36
CPSY2008-59
A programmable 9-contexts optically reconfigurable gate arrays and its writer
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)
pp. 37 - 40
CPSY2008-60
Perfect demonstration of a four-context Optically Reconfigurable Gate Array
Takayuki Mabuchi, Minoru Watanabe (Shizuoka Univ.)
pp. 41 - 44
CPSY2008-61
Comparison evaluation of an inversion/non-inversion dynamic optically reconfiguration architecture
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.)
pp. 45 - 50
CPSY2008-62
Circuit Partition Method with Time-multiplexed I/O
Tatsuki Isomura (Univ. of Kitakyushu), Masato Inagi (Hiroshima City Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC)
pp. 51 - 55
CPSY2008-63
An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
pp. 57 - 62
CPSY2008-64
A Proposal of the Computer Architecture for Numbers of Arbitrary Word Length
Shohei Hashimoto, Yuta Totsuka, Masamichi Makino, Hikaru Yasuda, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.)
pp. 63 - 68
CPSY2008-65
Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core
Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 69 - 74
CPSY2008-66
An Experimental Linux Cluster System for Tests
Koichi Kitano (Polytech.Univ.), Koji Teramoto (EHDO), Tadayoshi Horita (Polytech.Univ.)
pp. 75 - 79
CPSY2008-67
Extension of High Level Synthesis system CCAP for AMP multi-core system desin
Yoshiyuki Ishimori, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Nagoya Univ.), Hiroyuki Kanbara (ASTEM)
pp. 81 - 86
CPSY2008-68
A Tunable LSI Based on Timing Skew and Stall Adjustments
Yayumi Uehara, Mineo Kaneko (JAIST)
pp. 87 - 92
CPSY2008-69
Fast Module Placement in Floorplan-aware High-level Synthesis
Wataru Sato, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 93 - 98
CPSY2008-70
A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors
Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 99 - 104
CPSY2008-71
Automatic Equivalence Specification between Two Sequential Circuits in High-level Design
Jinmei Xu, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (University of Tokyo)
pp. 105 - 110
CPSY2008-72
Formal Verification Method for Protocol Transducer Using Automatically Generated Properties from Specification
Fei Gao, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo)
pp. 111 - 116
CPSY2008-73
Foreknown Regularity Arithmetic Processing Unit
Jin Sato, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.)
pp. 117 - 122
CPSY2008-74
Improvement of Search Efficiency by Principal Component Analysis for Analog Circuit Sizing of Operational Amplifier using Genetic Algorithm
Yuji Takehara (Toyohashi Univ. Tech.), Masanori Natsui (Tohoku Univ.), Yoshiaki Tadokoro (Toyohashi Univ. Tech.)
pp. 123 - 128
CPSY2008-75
A study for accurate RTL timing modeling
Shota Nakajima, Masahiro Fukui (Ritsumeikan Univ.)
pp. 129 - 134
CPSY2008-76
Interaction of Abstraction Processing for Creation of Ideas
-- An Electronic Brain like a thought of human being --
Tadayuki Hattori
pp. 135 - 140
CPSY2008-77
A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems
Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT)
pp. 141 - 146
CPSY2008-78
A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 147 - 152
CPSY2008-79
Combine operation pattern extraction from CDFG for DSP generation
Toshiyuki Kato, Takaaki Miyake, Shinichi Oomata, Hideto Nishikado, Hironori Yamauchi (Ritsumei Univ), Shiro Kobayashi (Asahi Kasei)
pp. 153 - 158
CPSY2008-80
Customizing of Domain-Specific and Compact Reconfigurable HW
Shogo Nakaya, Nobuki Kajihara, Toru Awashima (NEC)
pp. 159 - 164
CPSY2008-81
Delay Evaluation of 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation
Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ.)
pp. 165 - 170
CPSY2008-82
Implementation of Asynchronous Bus for GALS System
Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.)
pp. 171 - 176
CPSY2008-83
A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application
Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 177 - 182
CPSY2008-84
Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA
Masaru Kato, Toru Sano, Hideharu Amano (Keio Univ)
pp. 183 - 188
CPSY2008-85
An Architecture of Regular Expression Matching Machine for NIDS and Its FPGA Implementation
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ)
pp. 189 - 194
CPSY2008-86
An FPGA implementation of Gibbs sampling method towards high-speed motif search
Yuka Sato, Junko Tazawa, Toshiaki Miyazaki (Univ. of Aizu)
pp. 195 - 199
CPSY2008-87
Fast Solution of Link Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2
Taku Kihara, Sho Shimizu, Shan Gao, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Akifumi Watanabe (IPFlex)
pp. 201 - 206
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.