Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2009-69
A study of software development environment for dynamic-reconfigurable processor MuCCRA-3.
Kazuei Hironaka, Katsunobu Nishimura (Tokai Univ.), Hideharu Amano (Keio Univ.)
pp. 1 - 6
VLD2009-70
Reducing scheduling overheads in Dynamically Reconfigurable Processors
Ratna Krishnamoorthy (Univ of Tokyo), Keshavan Varadarajan, Mythri Alle (IISc), Ranjani Narayan (Morphing Machines), Masahiro Fujita (Univ of Tokyo), S K Nandy (IISc)
pp. 7 - 12
VLD2009-71
Evaluation of Hardware/Software Partitioning Method with Consideration of Software Parallelization
Junya Matsunaga, Michiaki Muraoka (Kochi Univ.), Dai Araki (InterDesign Technologies, Inc.)
pp. 13 - 18
VLD2009-72
Evaluation using Applications for RC-OS which supports Reconfigurable Computer System
Kazuya Tokunaga, Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ)
pp. 19 - 24
VLD2009-73
A network deliverable hw/sw complex, video codec
Ryosuke Kurogi, Kentaro Hanai, Hakaru Tamukoh, Yuuichi Kobayashi, Masatoshi Sekine (Tokyo Univ. of Agr and Tech.)
pp. 25 - 30
VLD2009-74
Development of Interdisciplinary Research Environment by Collaboration of e-Learning and Remote FPGA
Jaeseong Kim, Shingo Yoshizawa, Yusaku Kaneta, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.)
pp. 31 - 34
VLD2009-75
FPGA Implementation of Discrete Wavlet Transform Using Impulse C
Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic Kansei), Hideharu Amano (Keio Univ.)
pp. 35 - 40
VLD2009-76
An FPGA Implementation of Array Processor Performing 3D-DCT Effectively
Yuki Ikegaki, Hiroyuki Igarashi, Toshiaki Miyazaki, Stanislav G. Sedukhin (Univ. of Aizu)
pp. 41 - 46
VLD2009-77
Computer Aided Detection System Implementation for recognize cancer in Mammograms over a FPGA
Yessica Suarez Henandez (IPN/Univ. of Electro-Comm.), Sayaka Akioka, Tsutomu Yoshinaga, Volodymyr Ponomaryov, Gonzalo Duchen Sanchez (Univ. of Electro-Comm.)
pp. 47 - 52
VLD2009-78
A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure
Yuri Nishikawa (Keio Univ.), Michihiro Koibuchi (NII), Hiroki Matsutani (Tokyo Univ.), Hideharu Amano (Keio Univ.)
pp. 53 - 58
VLD2009-79
Design of Reconfigurable Logic Device based on Variable Grain Logic Cell
Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 59 - 64
VLD2009-80
Residue-Binary Conversion Using Signed-Digit Number Arithmetic
Changjun Jiang, Shugang Wei (Gunma Univ.)
pp. 71 - 76
VLD2009-81
Implementation Method and Performance Evaluation of Residue Arithmetic Circuits Using Signed-Digit Number Representation
Mingda Zhang, Shugang Wei (Gunma Univ.)
pp. 77 - 82
VLD2009-82
Hardware Specialization of Digital Filters for Vibration Control
Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda (Toyohashi Univ. of Tech.)
pp. 83 - 88
VLD2009-83
A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching
Norihiro Hashimoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 89 - 94
VLD2009-84
Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 95 - 99
VLD2009-85
Implementation of Power Reduction with Dynamically Dual-VDD Assignment to Dynamically Reconfigurable Processors Array
Yusuke Umahashi (Shibaura Inst. of Tech.), Toru Sano (Keio Univ.), Satoshi Koyama (Shibaura Inst. of Tech.), Yoshiki Saito, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 101 - 106
VLD2009-86
Granularity Optimization Method for AES Encryption Implementation on CUDA
Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA)
pp. 107 - 112
VLD2009-87
Effective Hardware Task Context Switching in Virtex-4 FPGAs
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.)
pp. 113 - 118
VLD2009-88
Hardware Acceleration in a Scalable FPGA System
Hironori Nakajo, Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.)
pp. 119 - 124
VLD2009-89
Expansion of Hardware in a Scalable FPGA System
Hironori Nakajo (Tokyo Univ. of Agr and Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech.), Satoshi Funada (e-trees.Japan, Inc), Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.)
pp. 125 - 130
VLD2009-90
An efficient hardware-oriented algorithm for regular expression matching based on parallel bit-distribution
Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.)
pp. 131 - 136
VLD2009-91
Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ)
pp. 137 - 142
VLD2009-92
A Packet Classifier Using a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Tech Corp.)
pp. 143 - 148
VLD2009-93
An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs
Satoshi Fujie, Ryoji Noji, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 149 - 154
VLD2009-94
Fault Recovery Technique for Softcore Processor using Partial Reconfiguration
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 155 - 160
VLD2009-95
An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level
Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.)
pp. 161 - 166
VLD2009-96
A remote dynamic optically reconfigurable gate array using a fiber array
Yumiko Ueno, Minoru Watanabe (Shizuoka Univ.)
pp. 167 - 170
VLD2009-97
Compensation method for photodiode characteristics variation using an analog configuration context
Yuji Aoyama, Minoru Watanabe (Shizuoka Univ.)
pp. 171 - 174
VLD2009-98
A programmable optically reconfigurable gate array with a silver-halide holographic memory
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)
pp. 175 - 179
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.