IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 110, Number 362

Reconfigurable Systems

Workshop Date : 2011-01-17 - 2011-01-18 / Issue Date : 2011-01-10

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Table of contents

RECONF2010-53
Behavior synthesis to hardware description language NSL of UML activity diagram
Toshihiro Kamikage, Ryota Yamazaki, Naohiko Shimizu (Tokai Univ)
pp. 1 - 6

RECONF2010-54
Implementation and evaluation of program development middleware for Cell Broadband Engine clusters
Toshiaki Kamata, Akihiro Shitara, Yuri Nishikawa (Keio Univ.), Masato Yoshimi (Doshisha Univ.), Hideharu Amano (Keio Univ.)
pp. 7 - 12

RECONF2010-55
Proposal and Preliminary Evaluation of System Diagnosis Technique for Large-scale Computer Network by Using Bayesian Network
Shingo Harashima (Keio Univ.), Hitoshi Yabusaki (Hitachi.LTD), Wataru Sakamoto (Osaka Univ.), Hiroaki Nishi (Keio Univ.)
pp. 13 - 18

RECONF2010-56
implementation of energy management sensor network and application to the home envirnment
Yukio Suhara, Tomohisa Nakabe, Hiroaki Nishi (Keio Univ.)
pp. 19 - 24

RECONF2010-57
Highly efficient mapping of electromagnetic wave interactions using the FDTD method for antenna designing on a CUDA-compatible GPU
Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto (Nagasaki Univ.)
pp. 25 - 30

RECONF2010-58
Parallelization of the channel width search for FPGA routing
Hiroomi Sawada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto)
pp. 31 - 36

RECONF2010-59
Approximated Variable Scheduling for High-Level Synthesis
Kousuke Sone, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 37 - 42

RECONF2010-60
A Heuristic Method using CODCs for Extraction of Maximum Observability Don't Care Set
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
pp. 43 - 48

RECONF2010-61
Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead
Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute)
pp. 49 - 54

RECONF2010-62
Design and check a ROHM 0.18μm chip with Alliance VHDL toolset -- Trial the layout and netlist check tools --
Tatsuya Hosokawa, Hiroshi Imai, Naohiko Shimizu (Tokai Univ.)
pp. 55 - 61

RECONF2010-63
Acceleration of Regression Test of Compilers by Program Merging
Kazushi Morimoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Yuki Uchiyama (K-OPT), Nobuyuki Hikichi (SRA, Inc)
pp. 63 - 67

RECONF2010-64
Automatic Retargeting of Binutils and GDB Based on Plug-in Method
Soichiro Taga (Kwansei Gakuin Univ.), Takahiro Kumura (NEC/Osaka Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 69 - 74

RECONF2010-65
Residue Arithmetic and FIR Filter Design Based on Minimal Signed-Digit Number Representation
Rui Chen, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 75 - 80

RECONF2010-66
Audio dynamic range compression using polynomial equations
Tatsuya Miyashita, Kazuhiro Motegi, Shugang Wei (Gunma Univ.)
pp. 81 - 85

RECONF2010-67
A Regular Expression Matching Circuit Based on Decomposed Automaton
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT)
pp. 105 - 110

RECONF2010-68
Encoding Methods of Multiple Data Streams for Hardware Compressors of Floating-Point Data
Kentaro Sano, Kazuya Katahira, Satoru Yamamoto (Tohoku Univ.)
pp. 111 - 116

RECONF2010-69
FPGA implementation of human detectin with HOG features and AdaBoost
Kazuhiro Negi, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 117 - 122

RECONF2010-70
A Fundamental Design of a Prototyping Environment to Apply Reconfigurable Logic Devices to Autonomous Recognition and Control Systems
Tomonori Izumi (Ritsumeikan Univ.)
pp. 123 - 126

RECONF2010-71
Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration
Naoko Yamada (Keio Univ.), Keisuke Iwai, Takakazu Kurokawa (NDA), Hideharu Amano (Keio Univ.)
pp. 127 - 132

RECONF2010-72
Feasibility of JHDL for Dynamically Reconfigurable Hardware Design
Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.)
pp. 133 - 138

RECONF2010-73
Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs
Yuji Masumitsu, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 139 - 144

RECONF2010-74
A Test Scheme for Interconnect of FPGA Focused on Switch Block Topology
Hiroki Yosho, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 145 - 150

RECONF2010-75
MEMS allowable alignment errors of a MEMS dynamic optically reconfigurable gate array
Hironobu Morita, Minoru Watanabe (Shizuoka Univ.)
pp. 151 - 156

RECONF2010-76
[Invited Talk] Design of Asynchronous Circuits with Bundled-data Implementation on FPGA
Hiroshi Saito (Univ. Aizu)
pp. 157 - 162

RECONF2010-77
Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator
Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.)
pp. 163 - 168

RECONF2010-78
Silent Large Datapath : A Ultra Low Power Accelarater
Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications)
pp. 169 - 174

RECONF2010-79
Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications)
pp. 175 - 180

RECONF2010-80
A Consideration of Window Join Operator over Data Streams by using FPGA
Yuta Terada, Takefumi Miyoshi (UEC), Hideyuki Kawashima (Univ. Tsukuba), Tsutomu Yoshinaga (UEC)
pp. 181 - 186

RECONF2010-81
A Validation of FPGA-based Many-core Simulator ScalableCore System
Shinya Takamaeda, Ryosuke Sasakawa, Kenji Kise (Tokyo Tech)
pp. 187 - 192

RECONF2010-82
Implementation and Evaluation of a Fast and Handy LCD Module Using an FPGA
Naoki Fujieda, Kenji Kise (Tokyo Tech)
pp. 193 - 198

RECONF2010-83
A Gateway and Remote Call Mechanisms for a PC-FPGA Hybrid Cluster
Masaki Kohata, Akira Uejima, Ryo Ozaki (Okayama Univ. of Sci.)
pp. 199 - 204

RECONF2010-84
Design of Dataflow Machine on Multiple FPGAs
Kenta Inakagata, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)
pp. 205 - 210

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan