IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 110, Number 413

Dependable Computing

Workshop Date : 2011-02-14 / Issue Date : 2011-02-07

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Table of contents

DC2010-59
The development of the DDR3 memory module tester used on memory test processor
Takeshi Asakawa, Satoshi Matsuno (Tokai Univ.), Hidekazu Tsuchiya (Hitachi), Tatsuya Seki, Shinichi Kmazawa (Techinica)
pp. 1 - 6

DC2010-60
Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors
Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.)
pp. 7 - 12

DC2010-61
An Analysis of Critical Paths for Field Testing with Process Variation Consideration
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ)
pp. 13 - 19

DC2010-62
Variation Aware Test Methodology Based on Statistical Static Timing Analysis
Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC)
pp. 21 - 26

DC2010-63
A Pattern Generation Method to Uniform Initial Temperature of Test Application
Emiko Kosoegawa, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST)
pp. 27 - 32

DC2010-64
Test Pattern Generation for Highly Accurate Delay Testing
Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST)
pp. 33 - 38

DC2010-65
A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models
Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
pp. 39 - 44

DC2010-66
Test Pattern Selection for Defect-Aware Test
Hiroshi Furutani, Takao Sakai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
pp. 45 - 50

DC2010-67
An Extended 2-D FPGA Array for CIP Circuit
Jiang Li, Kenichi Takahashi, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 51 - 56

DC2010-68
Dual Edge Triggered Flip-Flops for Blocking Noise Pulses on Data Signal Lines
Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 57 - 62

DC2010-69
Note on Area Overhead Reduction for Reconfigurable On-Chip Debug Circui
Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
pp. 63 - 68

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan