IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 111, Number 463

Silicon Device and Materials

Workshop Date : 2012-03-05 / Issue Date : 2012-02-27

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Table of contents

SDM2011-176
[Keynote Address] Development of Ultra Low Voltage Devices utilizing BEOL Process
Shin'ichiro Kimura (LEAP)
pp. 1 - 5

SDM2011-177
Basic Performance of a Logic-IP Compatible eDRAM with Cylinder Capacitors in Low-k/Cu BEOL Layers
Ippei Kume, Naoya Inoue, Ken'ichiro Hijioka, Jun Kawahara, Koichi Takeda, Naoya Furutake, Hiroki Shirai, Kenya Kazama, Shin'ichi Kuwabara, Msasatoshi Watarai, Takashi Sakoh, Toshifumi Takahashi, Takashi Ogura, Toshiji Taiji, Yoshiko Kasama (Renesas Electronics)
pp. 7 - 11

SDM2011-178
Highly Reliable BEOL-Transistor with oxygen-controlled InGaZnO channel and Gate/Drain Offset design
Kishou Kaneko, Naoya Inoue, Shinobu Saito, Naoya Furutake, Hiroshi Sunamura, Jun Kawahara, Masami Hane, Yoshihiro Hayashi (Renesas Electronics)
pp. 13 - 17

SDM2011-179
Initial Growth Observation of Multilayer Graphene on SiO2/Si substrate using Raman Spectroscopy and XPS
Yoshihiro Ojiro, Shuichi Ogawa (Tohoku Univ.), Manabu Inukai (JASRI), Motonobu Sato (AIST), Eiji Ikenaga, Takayuki Muro (JASRI), Mizuhisa Nihei (AIST), Yuji Takakuwa (Tohoku Univ.), Naoki Yokoyama (AIST)
pp. 19 - 24

SDM2011-180
Single-layered barrier/liner Co(W) by ALD/CVD for next generation ULSI-Cu interconnect
Hideharu Shimizu (Taiyo Nippon Sanso/Tokyo Univ.), Kohei Shima, Takeshi Momose (Tokyo Univ.), Yoshihiko Kobayashi (Taiyo Nippon Sanso), Yukihiro Shimogaki (Tokyo Univ.)
pp. 25 - 29

SDM2011-181
Evaluation of additives effects in copper electroplating solution by rapid exchange using microfluidic reactor
Takeyasu Saito, Yutaka Miyamoto, Sunao Hattori, Naoki Okamoto, Kazuo Kondo (Osaka Prefecture Univ.)
pp. 31 - 35

SDM2011-182
Formation of conformal barrier layer by electroless plating for TSV of 3D-LSI
Ryohei Arima, Hiroshi Miyake, Fumihiro Inoue, Tomohiro Shimizu, Shoso Shingubara (Kansai Univ.)
pp. 37 - 40

SDM2011-183
Influence of Via Stress on Surface Micro-roughness-induced Leakage Current in Through-Silicon Via Interconnects
Hideki Kitada (Univ. of Tokyo/Fujitsu Lab.), Nobuhide Maeda, Koji Fujimoto, Shoichi Kodama, Young Suk Kim (Univ. of Tokyo), Yoriko Mizushima (Univ. of Tokyo/Fujitsu Lab.), Tomoji Nakamura (Fujitsu Lab.), Takayuki Ohba (Univ. of Tokyo)
pp. 41 - 46

SDM2011-184
Characterization of Local Strain around Through Silicon Via Interconnect in Wafer-on-wafer Structures
Osamu Nakatsuka (Nagoya Univ.), Hideki Kitada, Young Suk Kim (Univ. of Tokyo), Yoriko Mizushima, Tomoji Nakamura (Fujitsu Lab.), Takayuki Ohba (Univ. of Tokyo), Shigeaki Zaima (Nagoya Univ.)
pp. 47 - 52

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan