Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2012-59
A Resource Sharing Method for Reconfigurable Systems with Java Virtual Machine
-- Programming in Instantiation --
Hitoki Ito, Kiyofumi Tanaka (JAIST)
pp. 1 - 5
VLD2012-60
Scalar replacement with exact analysis of array accesses
Hiroaki Takehana, Kenshu Seto (Tokyo City Univ.)
pp. 7 - 12
VLD2012-61
A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 13 - 18
VLD2012-62
Automated Identification of Performance Bottleneck on Embedded Systems for Architecture Exploration
Yuki Ando (Nagoya Univ.), Seiya Shibata (NEC), Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)
pp. 19 - 24
VLD2012-63
An Efficient ZDD Construction Method Using Recursive Specifications
Hiroaki Iwashita, Jun Kawahara (JST), Shin-ichi Minato (Hokkaido Univ.)
pp. 25 - 29
VLD2012-64
Partially-Programmable Circuits with CAMs
Atsushi Matsuo, Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida (Fujitsu Laboratories of Amerika)
pp. 31 - 36
VLD2012-65
[Invited Talk]
High Field Reliability Using Built-In Self Test
Seiji Kajihara (Kyutech)
pp. 37 - 42
VLD2012-66
[Invited Talk]
Development about LUMIX G Series, Digital Single-Lens Mirrorless Camera
Shinobu Husa (Panasonic)
p. 43
VLD2012-67
Secure Scan Architecture Using State Dependent Scan Flip Flop with Key-Based Configuration against Scan-Based Attack
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 45 - 50
VLD2012-68
Scan-based Attack against Camellia Cryptosystems
Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 51 - 56
VLD2012-69
A Delay Tuning Method of Programmable Delay Element with Two Delay Values for Yield Improvement
Hayato Mashiko, Yukihide Kohira (UoA)
pp. 57 - 62
VLD2012-70
Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation
Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.)
pp. 63 - 68
VLD2012-71
A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop
-- DICE ACFF --
Kanto Kubota, Masaki Masuda, Kazutoshi Kobayashi (KIT)
pp. 69 - 74
VLD2012-72
Variations and BTI-induced Aging Degradation on Commercial FPGAs
Shouhei Ishii, Kazutoshi Kobayashi (KIT)
pp. 75 - 80
VLD2012-73
A Method to Parallelize Simulated Annealing Algorithm by Generating Look-ahead Neighbor Solutions
Yusuke Ota, Kazuhito Ito (Saitama Univ.)
pp. 81 - 86
VLD2012-74
An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method
Yukihide Kohira (UoA), Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 87 - 92
VLD2012-75
An ILP Formulation of Placement and Routing for PLDs
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ)
pp. 93 - 98
VLD2012-76
A speculative execution method for indefinite loops in high level synthesis
Tatsuma Araki, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ)
pp. 99 - 104
VLD2012-77
A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation
Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu)
pp. 105 - 110
VLD2012-78
Controller Synthesis for Clock Improvement in Behavioral Synthesis
Ryoya Sobue (Ritsumeikan Univ.), Yuko Hara-Azumi (NAIST), Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 111 - 116
VLD2012-79
Accurate I/O Buffer Impedance Self-adjustment using Threshold Voltage and Temperature Sensors
Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.)
pp. 117 - 122
VLD2012-80
Analytical model of energy dissipation for comparing adder architectures
Nao Konishi, Kimiyoshi Usami (Shibaura I.T.)
pp. 123 - 128
VLD2012-81
Energy-efficient High-level Synthesis Considering Clock Design for HDR Architectures
Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 129 - 134
VLD2012-82
SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 135 - 140
VLD2012-83
Effective Orderings of Instances and Variable Assignments in SAT-based ATPG with Solution Reuse
Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 141 - 146
VLD2012-84
A Heuristic Algorithm for Operational Unit Binding in Transient Fault Tolerant Datapath Synthesis
Tatsuya Nakaso, Ryoko Ohkubo, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 147 - 152
VLD2012-85
Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning
Mineo Kaneko (JAIST)
pp. 153 - 158
VLD2012-86
A novel efficient data structure representing shared DAG patterns
Yusuke Matsunaga (Kyushu Univ.)
pp. 159 - 162
VLD2012-87
[Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects
Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics)
p. 163
VLD2012-88
On Handling Cell Placement with Adjacent Common Centroid Constraints for Analog IC Layout Design
Kunihiro Fujiyoshi, Keitaro Ue (TUAT)
pp. 165 - 170
VLD2012-89
Routability-oriented Common-Centroid Capacitor Array Generation
Jing Li, Bo Yang (Design Algorithm Lab.), Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 171 - 175
VLD2012-90
Performance evaluation of Via Programmable Logic VPEX using P&R tool
Taku Otani, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ), Masaya Yoshikawa (Meijo Univ), Takeshi Fujino (Ritsumeikan Univ)
pp. 177 - 182
VLD2012-91
A LSI-Package-Board co-evaluation of Power noise in the Digital LSI
Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ.)
pp. 183 - 188
VLD2012-92
Rational Function Approximation Using Vector Fitting and Equivalent Circuit Synthesis of Transmission Line Characteristics
Daisuke Honda, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)
pp. 189 - 194
VLD2012-93
High Sensitive Detection of Low S/N ratio Signal by Bistable Potential Circuit
Hisaaki Kanai, Wen Li, Kengo Imagawa, Masami Makuuchi, Yutaka Uematsu, Hideki Osaka (Hitachi, Ltd.)
pp. 195 - 200
VLD2012-94
A 3D FPGA-Array HPC System "Vocalise" and its Performance Evaluation
Yusuke Atsumari, Jiang Li, Hiromasa Kubo, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 201 - 206
VLD2012-95
Performance evaluation of a TCP/IP Hardware Stack Directly Connectable to WEB Application Circuit
Kotoko Fujita, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 207 - 212
VLD2012-96
The Fast Transient Analysis of The Power Distribution Network Modeled by Unstructured Meshes by Using Locally Implicit Latency Insertion Method (LIM)
Shingo Okada, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)
pp. 213 - 218
VLD2012-97
Explicit and Unconditionally Stable Finite Difference Scheme for the Fast Transient Analysis of the Power Distribution Network
Norio Nishizaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)
pp. 219 - 224
VLD2012-98
Control of Fine-Grain Power Gating by Detecting of the Virtual Ground Voltage
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 225 - 230
VLD2012-99
Energy Measurement and Analysis of ProcessingElement for Ultra Low Voltage
Sachio Anzai, Masaru Kudo, Yuya Ota, Kazuki Ota, Kimiyoshi Usami (Sibaura Inst. Tech.)
pp. 231 - 236
VLD2012-100
Neutron Induced Single Event Multiple Transients With Voltage Scaling and Body Biasing
Ryo Harada (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.)
pp. 237 - 241
VLD2012-101
Design of temperature and voltage monitoring circuit structure for field test
Wataru Tsumori, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT), Yukiya Miura (TMU)
pp. 243 - 248
VLD2012-102
A Scan-Out Power Reduction Method for Multi-Cycle BIST
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech)
pp. 249 - 254
VLD2012-103
A don't care filling method improve fault sensitization coverage on transition fault test set
Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ)
pp. 255 - 260
VLD2012-104
A Method to Estimate the Number of Don't-Care Bits with Netlist
Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (KIT)
pp. 261 - 266
VLD2012-105
A Study on Test Generation for Effective Test Compaction
Yukino Kusuyama, Tatuya Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.)
pp. 267 - 272
VLD2012-106
A Design Method of Fault-Secure Parallel Prefix Adders by Carry-Bit Duplication
Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.)
pp. 273 - 278
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.