Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2012-136
A Logic Simplification Algorithm with Multiple Stuck-at Faults for Error Tolerant Application
Junpei Kamei, Shingo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 1 - 6
VLD2012-137
Acceleration of current-threshold determination toward on-line IDDQ testing through parameter estimation
Michihiro Shintani, Takashi Sato (Kyoto Univ.)
pp. 7 - 12
VLD2012-138
Self-Compensation of Manufacturing Variability using On-Chip Sensors
Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
pp. 13 - 17
VLD2012-139
APR-based Legalization Method
Shota Hirae, Maho Ishikawa, Yasuhiro Takashima (Univ. of Kitakyusyu)
pp. 19 - 24
VLD2012-140
TSV-aware Analytical Placement
Koji Morita, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 25 - 29
VLD2012-141
Analytical Placement for Rectilinear Blocks
Tomoaki Gotanda, Yasuhiro Takashima (Univ. of Kitakyusyu)
pp. 31 - 36
VLD2012-142
The minimum perturbation placement realization for convex blocks
Hiroki Matsugano, Shota Hirae, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 37 - 42
VLD2012-143
An Automatic Nested Loop Pipelining method from C level behavior description
Masahiro Nambu, Takashi Kambe (Kinki Univ.)
pp. 43 - 48
VLD2012-144
An Acceleration method and its evaluation for Coarse Grained Reconfigurable Circuit Synthesis
Nobuyuki Araki, Takashi Kambe (Kinki Univ.)
pp. 49 - 54
VLD2012-145
High Level Resynthesis Approach of Reusable RTL Property
Msaato Tatsuoka, Mineo Kaneko (JAIST)
pp. 55 - 60
VLD2012-146
A Multi-Task Scheduling and Allocation for Highly Reliable Network-on-Chip
Hiroshi Saito (Univ. of Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC)
pp. 61 - 66
VLD2012-147
[Invited Talk]
Cyber-Physical Systems and LSI Design Technologies
Shinpei Kato, Masato Edahiro (Nagoya Univ.)
pp. 67 - 69
VLD2012-148
An Optimal Design Method for Input Signals of Small SoG-LCDs and Its Evaluation
Taichi Suizu, Shuji Tsukiyama (Chuo Univ.)
pp. 71 - 76
VLD2012-149
A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing
Kyosuke Shinoda, Atsushi Takahashi (Tokyo Inst. of Tech.)
pp. 77 - 82
VLD2012-150
A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors
Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 83 - 88
VLD2012-151
[Memorial Lecture]
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality
Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ.)
p. 89
VLD2012-152
[Memorial Lecture]
An Adaptive Current-Threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation
Michihiro Shintani, Takashi Sato (Kyoto Univ.)
p. 91
VLD2012-153
[Memorial Lecture]
Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis
Cong Hao, Song Chen, Takeshi Yoshimura (Waseda Univ.)
pp. 93 - 98
VLD2012-154
A worst-case-aware design methodology for oscillator-based true random number generator with stochastic behavior modeling
Takehiko Amaki, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Takao Onoye (Osaka Univ.)
pp. 99 - 104
VLD2012-155
Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating
Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.)
pp. 105 - 110
VLD2012-156
a design of COMET II processor as an embedded softcore processor
Kei Kimoto, Tomonori Izumi (Ritsumeikan Univ.)
pp. 111 - 116
VLD2012-157
Delay Analysis of Reconvergent Paths with Correlation
Masatsugu Hosoki, Hiroshi Sasaki, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 117 - 121
VLD2012-158
A Delay Control Circuit with Channel Length Decomposition and Its Application
Yuichi Toyota, Yuki Nakashima, Toru Fujimura, Shigetoshi Nakatake (Univ of Kitakyushu)
pp. 123 - 128
VLD2012-159
Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning
Mineo Kaneko (JAIST)
pp. 129 - 133
VLD2012-160
Probability Driven Hierarchical Fault Analysis System and its Implementation
Hikaru Goto, Masaya Yoshikawa (Meijo Univ.)
pp. 135 - 140
VLD2012-161
Trojan Circuit for Fault Analysis Countermeasure and its Implementation
Takaya Tsukadaira, Daisuke Matsushima (Meijo Univ.), Takeshi Kumaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.)
pp. 141 - 146
VLD2012-162
Robust Redundant Circuit Structure to Mitigate Wearout by Reversing Register Values
Shogo Okada, Masaki Masuda (Kyoto Inst. of Tech.), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
pp. 147 - 152
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.