Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2010] | [2011] | [2012] | [2013] | [2014] | [2015] | [2016] | [Japanese] / [English]
VLD2013-1
Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects
Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 1 - 6
VLD2013-2
A Floorplan Method by Simulated Annealing and Sequence-pair for Asynchronous Circuits with Bundled-data Implementation
Minoru Iizuka, Hiroshi Saito (Univ. of Aizu)
pp. 7 - 12
VLD2013-3
A Longest Path Algorithm for Differential Pair Net Considering Connectivity
Koji Yamazaki, Yukihide Kohira (Univ. of Aizu)
pp. 13 - 18
VLD2013-4
[Invited Talk]
A Note on Routing and Placement
Yoji Kajitani (JAIST)
pp. 37 - 41
VLD2013-5
Level Converter Design for Ultra Low Voltage Operation in Silicon-on-Thin-BOX MOSFET
Shohei Nakamura, Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 43 - 48
VLD2013-6
A Linear Interpolation Unit Using Selector Logics
Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 49 - 54
VLD2013-7
Data Dependence Relaxation Techniques for Reducing Iteration Intervals in Pipelined Loops
Shingo Kusakabe, Kenshu Seto (Tokyo City Univ.)
pp. 55 - 60
VLD2013-8
Scan-based Attack against Trivium Stream Cipher Using Scan Signatures
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 61 - 66
VLD2013-9
A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 67 - 72
VLD2013-10
SoC System Design Methodology with Fully-Coherent Cache
Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST)
pp. 73 - 78
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.