IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 114, Number 99

Dependable Computing

Workshop Date : 2014-06-20 / Issue Date : 2014-06-13

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Table of contents

DC2014-10
Development of a delay time measurement circuit by inserting buffers
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 1 - 6

DC2014-11
A method of LSI degradation estimation using ring oscillators
Tatsunori Ikeda, Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 7 - 14

DC2014-12
A X-Filling Method for Low-Capture-Power Scan Test Generation
Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara (Kyushu Inst. of Tech.)
pp. 15 - 20

DC2014-13
Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip
Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.)
pp. 21 - 26

DC2014-14
A Fault Tolerant Response Analyzer for Built-in Self-test
Yuki Fukazawa (Mie Univ.), Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 27 - 32

DC2014-15
Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication
Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.)
pp. 33 - 38

DC2014-16
A Binding Method for Hierarchical Testability Using Results of Test Environment Generation
Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.)
pp. 39 - 44

DC2014-17
An evaluation for Testability of Functional k-Time Expansion Models
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.)
pp. 45 - 50

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan