Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2019-44
Honda Koki, Wei Kaijie (Keio Univ.), Arai Masatoshi (Saitama Univ.), Amano Hideharu (Keio Univ.)
pp. 1 - 5
RECONF2019-45
Task offloading from vector processor to FPGA through PCIe connection
Kohei Hijikata (Tohoku Univ.), Tomohiro Ueno (RIKEN), Ryusuke Egawa, Hiroyuki Takizawa (Tohoku Univ.), Kentaro Sano (RIKEN)
pp. 7 - 11
RECONF2019-46
DDR4 SDRAM controller for real-time processing
So Haramura, Nobuyuki Yamasaki (Keio Univ.)
pp. 13 - 17
RECONF2019-47
A Consideration of NAT Traversal Function for MPI Runtime Environment on Android OS
Masahiro Nissato, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
pp. 19 - 24
RECONF2019-48
(See Japanese page.)
pp. 25 - 30
RECONF2019-49
Implementation and Evaluation of a Router on a Multi-FPGA System
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.)
pp. 31 - 36
RECONF2019-50
Performance Evaluation of Using Multi-Switch on a Multi-FPGA System
Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 37 - 42
RECONF2019-51
Increasing Test Variation for C Compilers by Equivalent Mutant Generation
Hiroki Maeda, Nagisa ishiura (Kwansei Gakuin Univ.)
pp. 43 - 48
RECONF2019-52
Mutation Fuzzing Based on Type Estimation of Data Items Utilizing Data Writer
Yoko Higuchi, Nagisa Ishiura, Namba Noriyuki (Kwansei Gakuin Univ.)
pp. 49 - 53
RECONF2019-53
On logic locking method with affine transformation
Yusuke Matsunaga (Kyushu Univ.)
pp. 55 - 59
RECONF2019-54
A Comparison of Filter for Convolutional Neural Network towards Hardware Implementation
Kosuke Akimoto, Youki Sada, Shimpei Sato, Hiroki Hakahara (Tokyo Tech)
pp. 61 - 66
RECONF2019-55
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks
Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (Titech)
pp. 67 - 72
RECONF2019-56
An FPGA Implementation of Monocular Depth Estimation
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech)
pp. 73 - 78
RECONF2019-57
An Efficient Cooperative Model Update using On-Device Learning
Rei Ito, Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
pp. 79 - 84
RECONF2019-58
A Light-Weight Reinforcement Learning using Online Sequential Learning
Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
pp. 85 - 90
RECONF2019-59
Memory access optimization for convolution with scheduling transformations of dependence graphs
Takayuki Todokoro, Kenshu Seto (TCU)
pp. 99 - 104
RECONF2019-60
Full Hardware Synthesis of FreeRTOS-Based Systems
Wakako Nakano, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)
pp. 105 - 110
RECONF2019-61
Binary Synthesis from RISC-V Executables
Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 111 - 115
RECONF2019-62
Design and implementation of a RISC-V computer system running Linux in Verilog HDL
Junya Miura, Hiromu Miyazaki, Kenji Kise (Tokyo Tech)
pp. 117 - 122
RECONF2019-63
Design and implementation of a RISC-V soft processor adopting five-stage pipelining
Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise (Tokyo Tech)
pp. 123 - 128
RECONF2019-64
(See Japanese page.)
pp. 129 - 134
RECONF2019-65
Study of a Simplified Digital Spiking Neuron and Its FPGA Implementation
Tomohiro Yoneda (NII)
pp. 135 - 140
RECONF2019-66
FPGA-based Stream Data Aggregation for Large Sliding-Windows
Masaki Osaka (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC)
pp. 141 - 146
RECONF2019-68
Accelerating 2D LiDAR SLAM Algorithm using FPGA
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
pp. 151 - 156
RECONF2019-69
(See Japanese page.)
p. 157
RECONF2019-70
A Case Study of Development of Signal Processing Systems with RFSoC
Ryohei Niwase (e-trees), Makoto Negoro, Yuta Kawai (Osaka Univ.), Takefumi Miyoshi (e-trees)
pp. 159 - 163
RECONF2019-71
Quantum control of electron spin qubit with RFSoC
Yuta Kawai, Takato Koide, Hiroki Imawaka, Koichiro Miyanishi (Osaka Univ.), Ryohei Niwase, Takefumi Miyoshi (e-trees), Makoto Negoro, Akinori Kagawa (Osaka Univ.)
pp. 165 - 167
RECONF2019-72
Virtual-Channel Implementation on Communication Circuit of FPGA Cluster by Qsys Interconnect
Naohisa Fukase, Akihisa Furuiti, Yasuyuki Miura, Tsukasa-Pierre Nakao (SIT)
pp. 169 - 174
RECONF2019-73
Parameter Aggregation using Software Switch for Multi-GPU Deep Learning
Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani (Keio Univ.)
pp. 175 - 180
RECONF2019-74
Implementation of high speed rainbow table generation using Keccak hashing algorithm on CUDA
Nguyen Dat Thuong, Keisuke Iwai, Takashi Matsubara, Takakazu Kurokawa (NDA)
pp. 181 - 186
RECONF2019-75
Prioritized Resource Management for Reservation Stations
Shota Nakabeppu, Nobuyuki Yamasaki (Keio Univ.)
pp. 187 - 191
RECONF2019-76
An FPGA implementation of arc-sine high-radix CORDIC algorithm
Hiroshi Matsuoka, Naofumi Takagi (Kyoto Univ.), Kazuyoshi Takagi (Mie Univ.)
pp. 193 - 197
RECONF2019-77
Edge detection algorithms using stochastic architectures for various images
Naoto Shinozaki, Kimiyoshi Usami (SIT)
pp. 199 - 204
RECONF2019-78
An Approach to Approximate Multiplier Optimization
Xinpei Zhang, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. Tokyo)
pp. 205 - 210
RECONF2019-79
Partial synthesis method based on Column-wise verification for integer multipliers
Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo)
pp. 211 - 216
RECONF2019-80
Measuring SER by Neutron Irradiation Between Volatile SRAM-based and Nonvolatile Flash-based FPGAs
Yuya Kawano, Yuto Tsukita, Jun Furuta, Kazutoshi Kobayashi (KIT)
pp. 217 - 222
RECONF2019-81
(See Japanese page.)
pp. 223 - 227
RECONF2019-82
(See Japanese page.)
pp. 229 - 232
RECONF2019-83
Study of stacked type logic LSI with fabrication technology of 3D flash memory.
Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst of Tech.)
pp. 233 - 238
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.