Online edition: ISSN 2432-6380
[TOP] | [2017] | [2018] | [2019] | [2020] | [2021] | [2022] | [2023] | [Japanese] / [English]
DC2020-69
A Study on a Method of Measuring Process Variations Considering the Effect of Wire Delay on FPGA
Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 1 - 6
DC2020-70
Hardware Trojan Detection by Learning Power Side Channel Signals Considering Random Process Variation
Michiko Inoue, Riaz-Ul-Haque Mian (NAIST)
pp. 7 - 11
DC2020-71
A Novel High Performance Scan-Test-Aware Hardened Latch Design
Ruijun Ma, Stefan Holst, Xiaoqing Wen (KIT), Aibin Yan (AHU), Hui Xu (AUST)
pp. 12 - 17
DC2020-72
Locating High Power Consuming Area in Logic parts Caused by Memory Size and Shapes
Daiki Takafuji, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech)
pp. 18 - 23
DC2020-73
(See Japanese page.)
pp. 24 - 29
DC2020-74
Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements
Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ)
pp. 30 - 35
DC2020-75
Fault Coverage Estimation Method in Multi-Cycle Testing
Norihiro Nakaoka, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas Electronics Corp.)
pp. 36 - 41
DC2020-76
A Test Generation Method Using Information of Easily Testable Functional Time Expansion Model
Kenta Nakamura, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.)
pp. 42 - 47
DC2020-77
A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
pp. 48 - 53
DC2020-78
(See Japanese page.)
pp. 54 - 58
DC2020-79
(See Japanese page.)
pp. 59 - 63
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.