IEICE Technical Report

Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2024-01-29 - 2024-01-30 / Issue Date : 2024-01-22

RECONF2023-83
Random number generation on the Rocket core with a built-in LFSR
Takayoshi Shikano, Shuichi Ichikawa (Toyohashi Tech.)
pp. 1 - 6

RECONF2023-84
Suppression of output bit width growth in AFE stochastic computing units
Daiki Seto, Naoki Fujieda (Aichi Inst. Tech.)
pp. 7 - 12

RECONF2023-85
(See Japanese page.)
pp. 13 - 18

RECONF2023-86
(See Japanese page.)
pp. 19 - 23

RECONF2023-87
[Invited Talk] Role of FPGAs in Quantum Network Architectures
Fumiaki Mizuno (Keio Univ.)
pp. 24 - 30

RECONF2023-88
(See Japanese page.)
pp. 31 - 34

RECONF2023-89
A Study of Low Latency Feedback Operation Architecture for Superconducting Qubit
Takefumi Miyoshi (QuEL/e-trees), Keisuke Koike (e-trees), Kazuhisa Ogawa, Ryo Matsuda, Hidehisa Shiomi (Osaka Univ.), Shinichi Morisaka (Osaka Univ./QuEL), Yutaka Tabuchi (RIKEN), Makoto Negoro (Osaka Univ.)
pp. 35 - 40

RECONF2023-90
An FPGA-based data compressor for state vector quantum simulators
Kaijie Wei, Hideharu Amano (Keio Univ.), Ryohei Niwase (Tsukuba Univ.), Takefumi Miyoshi (WasaLabo), Yoshiki Yamaguchi (Tsukuba Univ.)
pp. 41 - 46

RECONF2023-91
(See Japanese page.)
pp. 47 - 52

RECONF2023-92
High-speed division circuits using BCD codes
Fumiya Kanai, Yuki Tanaka (Gunma Univ.)
pp. 53 - 58

RECONF2023-93
Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis -- Toward comparative evaluation of latch-based and flip-flop-based circuits --
Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions)
pp. 59 - 64

RECONF2023-94
Comparison of latch-based circuit and flip-flop-based circuit in actual device
Kenji Takahashi, Tadaaki Tanimoto, Keizo Hiraga, Masayuki Hayashi, Takato Inoue, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions)
pp. 65 - 70

RECONF2023-95
Design space exploration for a CGRA architecture that efficiently handles the Systolic algorithm
Hajime Takishita (Keio Univ.), Takuya Kojima (UTokyo), Hideharu Amano (Keio Univ.)
pp. 71 - 75

RECONF2023-96
A Prototype Design of an Embedded Real-Time GPU
Takafumi Tarui, Nobuyuki Yamasaki (Keio Univ.)
pp. 76 - 80

RECONF2023-97
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems
Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)
pp. 81 - 86

RECONF2023-98
Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer
Sho Kishimoto, Nagisa Ishiukra (Kwansei Gakuin Univ.)
pp. 87 - 92

RECONF2023-99
Exploration of Acceleration of FPGA-based Linear Equation Solver using Approximate Division in Electronic Circuit Simulator
Naoki Kakine, Shuto Yuya, Tetsuo Hironaka, Atsushi Kubota (HCU)
pp. 93 - 98

RECONF2023-100
FPGA-Accelerated Random Forest for Real-Time IoT Intrusion Detection
Qingyu Zeng, Yuko Hara (Tokyo Tech)
pp. 99 - 104

RECONF2023-101
Comparison of Graph Data Structures for Breadth-First Search Accelerator HyGTA2
Jun Akimoto, Kazuya Tanigawa (Hiroshima City Univ), Kentaro Sano (Processor Research Team,RIKEN Center for Computational Science), Tetsuo Hironaka (Hiroshima City Univ)
pp. 105 - 106

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan